IP Library Granted Patent US 10,916,694
Granted Patent B2
US 10,916,694 · App. 16/255,754 · Granted Feb 9, 2021

Magnetoresistive random access memory (MRAM) device

Inventors: Hui-Lin Wang (Taipei, TW); Tai-Cheng Hou (Tainan, TW); Wei-Xin Gao (Tainan, TW); Fu-Yu Tsai (Tainan, TW); Chin-Yang Hsieh (Tainan, TW); Chen-Yi Weng (New Taipei, TW); Jing-Yin Jhang (Tainan, TW); Bin-Siang Tsai (Changhua County, TW); Kun-Ju Li (Tainan, TW); Chih-Yueh Li (Taipei, TW); Chia-Lin Lu (Taoyuan, TW); Chun-Lung Chen (Tainan, TW); Kun-Yuan Liao (Hisinchu, TW); Yu-Tsung Lai (Tainan, TW); Wei-Hao Huang (New Taipei, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L41/47H01L21/762H01L21/76802H01L43/02
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Quick Facts
Patent No.
US 10,916,694
App. No.
16/255,754
Granted
Feb 9, 2021
Kind
B2
Abstract

A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) on a substrate; forming a first ultra low-k (ULK) dielectric layer on the first MTJ; performing a first etching process to remove part of the first ULK dielectric layer and forming a damaged layer on the first ULK dielectric layer; and forming a second ULK dielectric layer on the damaged layer.

Claims (9)

1. A semiconductor device, comprising:

a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate;

a first ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ;

a first passivation layer in the first ULK dielectric layer and between the first MTJ and the second MTJ; and

a second ULK dielectric layer on the first ULK dielectric layer.

2. The semiconductor device of claim 1 , further comprising a second passivation layer between first ULK dielectric layer and the second ULK dielectric layer, wherein the first MTJ is between the first passivation layer and the second passivation layer.

3. The semiconductor device of claim 1 , further comprising a third passivation layer between first ULK dielectric layer and the second ULK dielectric layer, wherein the second MTJ is between the first passivation layer and the third passivation layer.

4. The semiconductor device of claim 1 , wherein top surfaces of the first ULK dielectric layer and the first passivation layer are coplanar.

5. The semiconductor device of claim 1 , wherein the first ULK dielectric layer and the first passivation layer comprise different materials.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2019
From: WANG, HUI-LIN; HOU, TAI-CHENG; GAO, WEI-XIN; TSAI, FU-YU; HSIEH, CHIN-YANG; WENG, CHEN-YI; JHANG, JING-YIN; TSAI, BIN-SIANG; LI, KUN-JU; LI, CHIH-YUEH; LU, CHIA-LIN; CHEN, CHUN-LUNG; LIAO, KUN-YUAN; LAI, YU-TSUNG; HUANG, WEI-HAO
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 048117/0906 →
Priority Claims (1)
CN 2018 1 1612412 · Dec 27, 2018 · national
Continuity (1)
Related Publication 20200212290A1 · Jul 2, 2020