IP Library › Granted Patent US 10,886,905
Granted Patent B1
US 10,886,905 · App. 16/256,390 · Granted Jan 5, 2021

Signal generator with coherent phase output

Inventors: Duan Zhao (Utrecht, NL); Michail Papamichail (Eindoven, NL); Joek de Haas (Veldhoven, NL)
Assignee: Dialog Semiconductor B.V.
H03K5/15006H03L7/0992H03L7/0994
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Quick Facts
Patent No.
US 10,886,905
App. No.
16/256,390
Granted
Jan 5, 2021
Kind
B1
Abstract

A signal generator and a method which provides a source signal with a coherent phase at arbitrary times is presented. There is provided a signal generator for generating a source signal based on a reference signal. The signal generator has a phase setting circuit with a memory circuit operable between a plurality of states. The memory circuit has a phase setting input adapted to receive a phase setting value to set the memory circuit to a known state. The signal generator is adapted to load the phase setting value at a specific time to control a phase of the source signal.

Claims (26)

1. A signal generator for generating a source signal based on a reference signal, the signal generator comprising,

a phase setting circuit comprising a memory circuit operable between a plurality of states;

wherein the memory circuit comprises a phase setting input adapted to receive a pre-determined phase setting value to set the memory circuit to a known state;

wherein the source signal has a phase difference with respect to the reference signal;

wherein upon reset, the signal generator is adapted to load a selected pre-determined phase setting value at a specific time to set the phase difference to a chosen value, so that the phase of the source signal follows a chosen phase trajectory;

wherein the signal generator is operable between arbitrary periods in time, the arbitrary periods comprising a first period during which the signal generator provides a first source signal, and a second period during which the signal generator provides a second source signal;

wherein the signal generator further comprises a calculator configured to calculate the pre-determined phase setting value as a function of a time difference between a start of the first period and a start of the second period, a frequency of operation of the signal generator and a frequency of the reference signal.

2. The signal generator as claimed in claim 1 , wherein the signal generator comprises a signal circuit coupled to the phase setting circuit; the signal circuit being adapted to generate the source signal based on the reference signal.

3. The signal generator as claimed in claim 1 , wherein the pre-determined phase setting value is associated with a known phase difference between the reference signal and the source signal.

4. The signal generator as claimed in claim 1 , wherein between the first period and the second period the signal generator is deactivated and provides no source signal.

5. The signal generator as claimed in claim 1 , wherein the selected pre-determined phase setting value is based on a phase trajectory of the first source signal.

6. The signal generator as claimed in claim 1 , wherein upon loading the selected pre-determined phase setting value, the second source signal is set to the chosen phase trajectory.

7. The signal generator as claimed in claim 1 , wherein the memory circuit further comprises a data input for receiving a data signal, and a load input for receiving a load signal to load the selected pre-determined phase setting value from the phase setting input.

8. The signal generator as claimed in claim 1 , wherein the memory circuit further comprises a clock input for receiving a clock signal.

9. The signal generator as claimed in claim 7 , wherein the phase setting circuit further comprises an adder adapted to provide the data signal to the memory circuit.

10. A method of generating a source signal based on a reference signal, wherein the source signal has a phase difference with respect to the reference signal, the method comprising,

providing a signal generator with a phase setting circuit comprising a memory circuit operable between a plurality of states;

providing a pre-determined phase setting value associated with a known state of the memory circuit; and

upon reset of the signal generator, selecting and loading the pre-determined phase setting value into the memory circuit at a specific time to set the phase difference to a chosen value, so that the phase of the source signal follows a chosen phase trajectory;

wherein the signal generator is operable between arbitrary periods in time, the arbitrary periods comprising a first period during which the signal generator provides a first source signal, and a second period during which the signal generator provides a second source signal;

wherein the signal generator further comprises a calculator configured to calculate the pre-determined phase setting value as a function of a time difference between a start of the first period and a start of the second period, a frequency of operation of the signal generator and a frequency of the reference signal.

11. The method as claimed in claim 10 , wherein the pre-determined phase setting value is associated with a known phase difference between the reference signal and the source signal.

12. The method as claimed in claim 10 , wherein between the first period and the second period the signal generator is deactivated and provides no source signal.

13. The method as claimed in claim 10 , comprising identifying a phase trajectory of the first source signal and calculating the pre-determined phase setting value based on the first phase trajectory.

14. The method as claimed in claim 10 , wherein upon loading the selected pre-determined phase setting value, the second source signal is set to the chosen phase trajectory.

15. The method as claimed in claim 10 , wherein the memory circuit comprises a data input for receiving a data signal, and a load input for receiving a load signal to load the selected pre-determined phase setting value from the phase setting input.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2019
From: ZHAO, DUAN; PAPAMICHAIL, MICHAIL; DE HAAS, JOEK
To: DIALOG SEMICONDUCTOR B.V.
Reel/Frame 048380/0467 →