Semiconductor device and manufacturing method thereof
View Patent ↗A semiconductor device includes a substrate, a dielectric fin, a gate, and a high-k dielectric layer. The dielectric fin is above the substrate and extending along a first direction. The gate is above the substrate and extends in a second direction that intersects the first direction. The high-k dielectric layer is vertically above the dielectric fin. The gate is over a sidewall and a bottom surface of the high-k dielectric layer.
1. A semiconductor device, comprising:
a substrate;
a dielectric fin above the substrate and extending along a first direction;
a gate electrode above the substrate and extending in a second direction that intersects the first direction; and
a high-k dielectric layer wrapping around a top surface and opposite sidewalls of the dielectric fin, wherein the gate electrode is in direct contact with a sidewall and a portion of a bottom surface of the high-k dielectric layer.
2. The semiconductor device of claim 1 , wherein the high-k dielectric layer is in contact with the dielectric fin.
3. The semiconductor device of claim 1 , wherein the high-k dielectric layer straddles the dielectric fin.
4. The semiconductor device of claim 1 , wherein a width of the high-k dielectric layer is greater than a width of the gate electrode along the first direction.
5. The semiconductor device of claim 1 , wherein a top surface of the high-k dielectric layer is higher than a top surface of the gate electrode.
6. The semiconductor device of claim 1 , wherein a portion of the gate electrode is vertically between the high-k dielectric layer and the substrate.
7. The semiconductor device of claim 1 , further comprising a gate dielectric layer between the gate electrode and the substrate and in contact with the bottom surface of the high-k dielectric layer.
8. The semiconductor device of claim 1 , further comprising a hard mask above the gate electrode and in contact with the sidewall of the high-k dielectric layer.
9. The semiconductor device of claim 8 , wherein a top surface of the high-k dielectric layer is coplanar with a top surface of the hard mask.
10. The semiconductor device of claim 8 , wherein the high-k dielectric layer comprises a material different from that of the hard mask.
11. The semiconductor device of claim 8 , wherein the high-k dielectric layer comprises a material that is substantially the same as a material of the hard mask.
12. A semiconductor device, comprising:
a substrate;
a semiconductor fin extending upwardly from the substrate;
a dielectric fin extending upwardly above the substrate and along a lengthwise direction of the semiconductor fin;
a high-k dielectric layer over the dielectric fin, wherein the dielectric fin has a top portion embedded in the high-k dielectric layer;
a gate electrode extending across the semiconductor fin to reach the dielectric fin and over a sidewall and a portion of a bottom surface of the high-k dielectric layer; and
a gate dielectric layer sandwiched between the semiconductor fin and the gate electrode and having a longitudinal end below the bottom surface of the high-k dielectric layer and in contact with a sidewall of the dielectric fin.
13. The semiconductor device of claim 12 , wherein the high-k dielectric layer is in contact with a sidewall of the dielectric fin.
14. The semiconductor device of claim 12 , wherein a width of the high-k dielectric layer is greater than a width of the dielectric fin along a lengthwise direction of the gate electrode.
15. The semiconductor device of claim 12 , wherein the bottom surface of the high-k dielectric layer is lower than a top surface of the semiconductor fin.
16. The semiconductor device of claim 12 , wherein the gate dielectric layer that has a first portion vertically between the substrate and the gate electrode and has a second portion vertically between the substrate and the high-k dielectric layer.
17. The semiconductor device of claim 12 , further comprising a source/drain via in contact with a top surface of the high-k dielectric layer.
18. A semiconductor device, comprising:
a substrate;
a semiconductor fin extending upwardly from the substrate;
a shallow trench isolation laterally surrounding the semiconductor fin;
a dielectric fin partially embedded in the shallow trench isolation, extending along a lengthwise direction of the semiconductor fin, having a topmost end in a position level with a topmost end of the semiconductor fin, and a bottommost end spaced apart from the substrate;
a high-k dielectric layer straddling the dielectric fin and spaced apart from the shallow trench isolation; and
a gate electrode extending across the semiconductor fin and over a sidewall and a portion of a bottom surface of the high-k dielectric layer, wherein the gate electrode has a stepped sidewall structure having a lower sidewall contacting a sidewall of the dielectric fin, and an upper sidewall laterally set back from the lower sidewall, and the upper sidewall contacts a sidewall of the high-k dielectric layer.
19. The semiconductor device of claim 18 , wherein a greatest dimension of the high-k dielectric layer is greater than a width of the dielectric fin in a lengthwise direction of the gate electrode from a top view.
20. The semiconductor device of claim 18 , wherein a first portion of the high-k dielectric layer above the dielectric fin has a width greater than a second portion of the high-k dielectric layer above the gate electrode along the lengthwise direction of the semiconductor fin from a top view.