Buried channel structure integrated with non-planar structures
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, buried channel structures integrated with non-planar structures. In an example, an integrated circuit structure includes a first fin structure and a second fin structure above a substrate. A gate structure is on a portion of the substrate directly between the first fin structure and the second fin structure. A source region is in the first fin structure. A drain region is in the second fin structure.
1. An integrated circuit structure, comprising:
a first fin structure and a second fin structure protruding through a dielectric layer above a semiconductor substrate, the dielectric layer having an uppermost surface;
a gate structure directly on a portion of the semiconductor substrate, the portion of the semiconductor substrate between the first fin structure and the second fin structure, the gate structure comprising a gate electrode having a bottommost surface below the uppermost surface of the dielectric layer;
a source region in the first fin structure; and
a drain region in the second fin structure.
2. The integrated circuit structure of claim 1 , wherein the first fin structure comprises a first pair of silicon fins, and wherein the second fin structure comprises a second pair of silicon fins.
3. The integrated circuit structure of claim 1 , wherein the first fin structure is over a first well region in the semiconductor substrate, and the second fin structure is over a second well region in the semiconductor substrate.
4. The integrated circuit structure of claim 3 , wherein the gate structure is over a buried doped region in the semiconductor substrate.
5. The integrated circuit structure of claim 4 , wherein the first well region, the second well region, and the buried doped region have an N-type conductivity.
6. The integrated circuit structure of claim 1 , further comprising:
a third fin structure above the semiconductor substrate, the third fin structure adjacent the second fin structure.
7. The integrated circuit structure of claim 6 , wherein the third fin structure comprises a pair of silicon fins.
8. The integrated circuit structure of claim 6 , wherein the third fin structure is over a well region in the semiconductor substrate, the well region having a P- type conductivity.
9. The integrated circuit structure of claim 6 , further comprising a tap diffusion region in the third fin structure.
10. An integrated circuit structure, comprising:
a buried channel device, comprising:
a source region in a first fin structure protruding through a dielectric layer above a semiconductor substrate, the dielectric layer having an uppermost surface;
a drain region in a second fin structure protruding through the dielectric layer above the semiconductor substrate; and
a first gate structure between the source region and the drain region, the first gate structure directly on a substantially planar region of the semiconductor substrate between the first fin structure and the second fin structure, the gate structure comprising a gate electrode having a bottommost surface below the uppermost surface of the dielectric layer; and
a non-planar device comprising a second gate structure over a plurality of fins above the semiconductor substrate.
11. The integrated circuit structure of claim 10 , wherein the buried channel device is an N-type buried channel device, and the non-planar device is an N-type non-planar device.
12. The integrated circuit structure of claim 10 , wherein the first gate structure has an uppermost surface co-planar with an uppermost surface of the second gate structure.
13. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first fin structure and a second fin structure protruding through a dielectric layer above a semiconductor substrate, the dielectric layer having an uppermost surface;
a gate structure directly on a portion of the semiconductor substrate, the portion of the semiconductor substrate between the first fin structure and the second fin structure, the gate structure comprising a gate electrode having a bottommost surface below the uppermost surface of the dielectric layer;
a source region in the first fin structure; and
a drain region in the second fin structure.
14. The computing device of claim 13 , further comprising:
a memory coupled to the board.
15. The computing device of claim 13 , further comprising:
a communication chip coupled to the board.
16. The computing device of claim 13 , further comprising:
a camera coupled to the board.
17. The computing device of claim 13 , further comprising:
a battery coupled to the board.
18. The computing device of claim 13 , further comprising:
an antenna coupled to the board.
19. The computing device of claim 13 , wherein the component is a packaged integrated circuit die.
20. The computing device of claim 13 , wherein the component is selected from the group consisting of a processor, a communications chip, and a digital signal processor.
21. The computing device of claim 13 , wherein the computing device is selected from the group consisting of a mobile phone, a laptop, a desk top computer, a server, and a set-top box.