Semiconductor package and fabricating method thereof
A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.
1. A semiconductor device comprising:
a front side redistribution structure (“FSRDS”) comprising a first FSRDS dielectric layer;
a semiconductor die comprising a front die side and a back die side, the front die side comprising a conductive pad, the front die side facing toward and coupled to a top side of the front side redistribution structure;
a stacked component interconnection structure comprising a top side and a bottom side, the bottom side of the stacked component interconnection structure coupled to the top side of the front side redistribution structure, the top side of the stacked component interconnection structure extending vertically at least as high as the back die side;
an encapsulating material on the top side of the front side redistribution structure and laterally surrounding the semiconductor die;
a back side redistribution structure (“BSRDS”) comprising:
a first BSRDS dielectric layer on a top side of the encapsulating material;
a first BSRDS conductive via extending entirely through the first BSRDS dielectric layer and coupled to the top side of the stacked component interconnection structure;
a first BSRDS trace on a top side of the first BSRDS dielectric layer;
a second BSRDS dielectric layer on the top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering lateral sides of first BSRDS trace and a top side of the first BSRDS trace;
a second BSRDS conductive via coupled to the top side of first BSRDS trace and extending vertically from the top side of the first BSRDS trace to a top side of the second BSRDS dielectric layer; and
a top side component connection pad coupled to the second BSRDS conductive via; and an underfill material directly vertically between the semiconductor die and the FSRDS.
2. The semiconductor device of claim 1 , wherein the first BSRDS conductive via comprises a single layer of metal that extends entirely through the first BSRDS dielectric layer.
3. The semiconductor device of claim 2 , wherein the first BSRDS conductive via runs only in a substantially vertical direction through the first BSRDS dielectric layer.
4. The semiconductor device of claim 1 , wherein the first BSRDS dielectric layer is free of any embedded trace that runs in a horizontal direction.
5. The semiconductor device of claim 1 , wherein the underfill material is different from the encapsulating material.
6. The semiconductor device of claim 1 , wherein:
the front side redistribution structure comprises a second FSRDS dielectric layer and a third FSRDS dielectric layer; and
each of the first FSRDS dielectric layer, the second FSRDS dielectric layer, and the third FSRDS dielectric layer laterally surrounds a plurality of conductive layers that are positioned on different vertical levels.
7. The semiconductor device of claim 1 , wherein:
the front side redistribution structure comprises:
a lower FSRDS dielectric layer; and
a ball contact comprising a plated pad layer embedded in the lower FSRDS dielectric layer; and
no part of the plated pad layer is lower than a bottom side of the lower FSRDS dielectric layer.
8. The semiconductor device of claim 1 , wherein:
the front side redistribution structure comprises:
a lower FSRDS dielectric layer; and
a ball contact comprising a plated pad layer embedded in the lower FSRDS dielectric layer; and
a side of the plated pad layer is coplanar with a side of the lower FSRDS dielectric layer.
9. The semiconductor device of claim 1 , wherein:
the encapsulating material covers the back die side; and
the encapsulating material comprises a top side that is coplanar with the top side of the stacked component interconnection structure.
10. A semiconductor device comprising:
a front side redistribution structure (“FSRDS”) comprising:
a first FSRDS dielectric layer;
a second FSRDS dielectric layer; and
a third FSRDS dielectric layer,
wherein each of the first FSRDS dielectric layer, second FSRDS dielectric layer, and third FSRDS dielectric layer laterally surround a plurality of FSRDS conductive layers on different vertical levels;
a first semiconductor die comprising a front die side and a back die side, the front die side comprising a conductive pad, the front die side facing toward and coupled to a top side of the front side redistribution structure;
a first stacked component interconnection structure comprising a top side and a bottom side, the bottom side of the first stacked component interconnection structure coupled to the top side of the front side redistribution structure, the top side of the first stacked component interconnection structure extending vertically at least as high as the back die side;
a second stacked component interconnection structure comprising a top side and a bottom side, the bottom side of the second stacked component interconnection structure coupled to the top side of the front side redistribution structure, the top side of the second stacked component interconnection structure extending vertically at least as high as the back die side;
an encapsulating material on the top side of the front side redistribution structure and laterally surrounding the first semiconductor die;
a back side redistribution structure (“BSRDS”) comprising:
a first BSRDS dielectric layer on a top side of the encapsulating material;
a first BSRDS conductive via extending entirely through the first BSRDS dielectric layer and coupled to the top side of the first stacked component interconnection structure;
a first BSRDS trace on a top side of the first BSRDS dielectric layer;
a second BSRDS dielectric layer on the top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering lateral sides of first BSRDS trace and a top side of the first BSRDS trace; and
an upper via that extends through the second BSRDS dielectric layer from a top side of the second BSRDS dielectric layer to the top side of the first BSRDS trace; and an underfill material directly vertically between the semiconductor die and the FSRDS.
11. The semiconductor device of claim 10 , comprising a second semiconductor die, wherein the first and second semiconductor dies are positioned laterally between the first and second stacked component interconnection structures.
12. The semiconductor device of claim 11 , wherein the second semiconductor die is entirely laterally displaced from the first semiconductor die.
13. The semiconductor device of claim 11 , wherein a portion of the encapsulating material is directly between the first and second semiconductor dies.
14. The semiconductor device of claim 11 , wherein a portion of the underfill material is material directly between the first and second semiconductor dies, the underfill material comprising a surface contacted by the encapsulating material.
15. The semiconductor device of claim 10 , wherein the underfill material is different from the encapsulating material.
16. The semiconductor device of claim 10 , wherein the underfill material comprises a lateral side that is contacted by the encapsulating material.
17. The semiconductor device of claim 10 , comprising a top side component interconnection structure comprising a lower portion that is positioned in the upper via and an upper portion that is above the upper via.
18. A method of making a semiconductor device, the method comprising:
providing a front side redistribution structure (“FSRDS”) comprising a first FSRDS dielectric layer;
providing a semiconductor die comprising a front die side and a back die side, the front die side comprising a conductive pad, the front die side facing toward and coupled to a top side of the front side redistribution structure;
providing a stacked component interconnection structure comprising a top side and a bottom side, the bottom side of the stacked component interconnection structure coupled to the top side of the front side redistribution structure, the top side of the stacked component interconnection structure extending vertically at least as high as the back die side;
providing an encapsulating material on the top side of the front side redistribution structure and laterally surrounding the semiconductor die;
providing a back side redistribution structure (“BSRDS”) comprising:
a first BSRDS dielectric layer on a top side of the encapsulating material;
a first BSRDS conductive via extending entirely through the first BSRDS dielectric layer and coupled to the top side of the stacked component interconnection structure;
a first BSRDS trace on a top side of the first BSRDS dielectric layer;
a second BSRDS dielectric layer on the top side of the first BSRDS dielectric layer, the second BSRDS dielectric layer covering lateral sides of first BSRDS trace and a top side of the first BSRDS trace;
a second BSRDS conductive via coupled to the top side of first BSRDS trace and extending vertically from the top side of the first BSRDS trace to a top side of the second BSRDS dielectric layer; and
a top side component connection pad coupled to the second BSRDS conductive via; and forming an underfill material directly vertically between the semiconductor die and the FSRDS.
19. The method of claim 18 , wherein the underfill material is different from the encapsulating material.
20. The method of claim 18 , wherein:
the front side redistribution structure comprises a second FSRDS dielectric layer and a third FSRDS dielectric layer; and
each of the first FSRDS dielectric layer, the second FSRDS dielectric layer, and the third FSRDS dielectric layer laterally surrounds a plurality of conductive layers that are positioned on different vertical levels.