IP Library Granted Patent US 11,550,977
Granted Patent B2
US 11,550,977 · App. 16/261,113 · Granted Jan 10, 2023

Apparatus and method for quantum performance and/or error correction enhancement using multi-qubit gates

Inventors: Sahar Daraeizadeh (Lake Oswego, OR); Anne Matsuura (Portland, OR); Xiang Zou (Hillsboro, OR); Sonika Johri (Portland, OR)
Assignee: INTEL CORPORATION
G06F30/30G06F11/1068G06N10/00G06N10/70G11C29/52
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Quick Facts
Patent No.
US 11,550,977
App. No.
16/261,113
Granted
Jan 10, 2023
Kind
B2
Abstract

Apparatus and method for replacing portions of a quantum circuit with multi-qubit gates. For example, one embodiment of an apparatus comprises: a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

Claims (38)

1. An apparatus comprising:

a quantum circuit analyzer to evaluate an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification, the quantum circuit analyzer to generate results of the evaluation; and

a quantum circuit generator to generate a new quantum circuit specification based on the results of the evaluation generated by the quantum circuit analyzer, the quantum circuit generator to generate the new quantum circuit specification by, at least in part, replacing the one or more sub-circuits of the original quantum circuit specification with one or more multi-qubit gates.

2. The apparatus of claim 1 wherein the results of the evaluation comprise an indication of the one or more multi-qubit gates to be used to replace the one or more sub-circuits.

3. The apparatus of claim 2 wherein the quantum circuit analyzer is to further evaluate a specified quantum error correction code to generate the results, wherein the one or more multi-qubit gates are selected by the quantum circuit analyzer to implement the specified quantum error correction code.

4. The apparatus of claim 1 further comprising:

a quantum circuit database to store data associating a plurality of quantum circuit/sub-circuit specifications with a plurality of multi-qubit gates;

wherein the quantum circuit analyzer is to query the quantum circuit database as part of its evaluation of the original quantum circuit specification to generate the results.

5. The apparatus of claim 1 wherein the quantum circuit analyzer is to select the one or more sub-circuits of the original quantum circuit specification for replacement by the one or more multi-qubit gates based on the one or more sub-circuits having gates which are repeatedly applied in series.

6. The apparatus of claim 5 wherein all of the gates of a first multi-qubit gate selected by the quantum circuit analyzer are capable of being implemented in parallel.

7. The apparatus of claim 6 wherein the first multi-qubit gate is operable on a set of data qubits and a set of ancilla qubits.

8. The apparatus of claim 7 wherein the set of ancilla qubits are to protect data integrity of the data qubits.

9. A method comprising:

evaluating an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification to generate results identifying one or more multi-qubit gates; and

generating, by a quantum circuit generator, a new quantum circuit specification based on the results, the new quantum circuit specification comprising the one or more sub-circuits of the original quantum circuit specification replaced with the one or more multi-qubit gates.

10. The method of claim 9 wherein the results of the evaluation comprise an indication of the one or more multi-qubit gates to be used to replace the one or more sub-circuits.

11. The method of claim 10 wherein evaluating further comprises:

analyzing a specified quantum error correction code to generate the results, wherein the one or more multi-qubit gates are selected in view of the specified quantum error correction code.

12. The method of claim 9 further comprising:

storing data in a database associating a plurality of quantum circuit/sub-circuit specifications with a plurality of multi-qubit gates;

wherein evaluating further comprises querying the database to generate the results.

13. The method of claim 9 wherein the one or more sub-circuits of the original quantum circuit specification are selected for replacement by the one or more multi-qubit gates based on the one or more sub-circuits having gates which are repeatedly applied in series.

14. The method of claim 13 wherein all of the gates of a first multi-qubit gate are capable of being implemented in parallel.

15. The method of claim 14 wherein the first multi-qubit gate is operable on a set of data qubits and a set of ancilla qubits.

16. The method of claim 15 wherein the set of ancilla qubits are to protect data integrity of the data qubits.

17. A non-transitory machine-readable medium having program code stored thereon which, when executed by a machine, causes the machine to perform the operations of:

evaluating an original quantum circuit specification including one or more sub-circuits of the original quantum circuit specification to generate results identifying one or more multi-qubit gates; and

generating, by a quantum circuit generator, a new quantum circuit specification based on the results, the new quantum circuit specification comprising the one or more sub-circuits of the original quantum circuit specification replaced with the one or more multi-qubit gates.

18. The non-transitory machine-readable medium of claim 17 wherein the results of the evaluation comprise an indication of the one or more multi-qubit gates to be used to replace the one or more sub-circuits.

19. The non-transitory machine-readable medium of claim 18 wherein evaluating further comprises:

analyzing a specified quantum error correction code to generate the results, wherein the one or more multi-qubit gates are selected in view of the specified quantum error correction code.

20. The non-transitory machine-readable medium of claim 17 further comprising:

storing data in a database associating a plurality of quantum circuit/sub-circuit specifications with a plurality of multi-qubit gates;

wherein evaluating further comprises querying the database to generate the results.

21. The non-transitory machine-readable medium of claim 17 wherein the one or more sub-circuits of the original quantum circuit specification are selected for replacement by the one or more multi-qubit gates based on the one or more sub-circuits having gates which are repeatedly applied in series.

22. The non-transitory machine-readable medium of claim 21 wherein all of the gates of a first multi-qubit gate are capable of being implemented in parallel.

23. The non-transitory machine-readable medium of claim 22 wherein the first multi-qubit gate is operable on a set of data qubits and a set of ancilla qubits.

24. The non-transitory machine-readable medium of claim 23 wherein the set of ancilla qubits are to protect data integrity of the data qubits.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 29, 2019
From: DARAEIZADEH, SAHAR; MATSUURA, ANNE; ZOU, XIANG; JOHRI, SONIKA
To: INTEL CORPORATION
Reel/Frame 050856/0840 →
Continuity (1)
Related Publication 20200242208A1 · Jul 30, 2020
Cited By (2)
US 12,210,936 US 12,261,627