Indefinitely expandable high-capacity data switch
A data switch for a packet data switch includes switching nodes connected to each other in an interconnecting matrix, providing a multiplicity of data paths between an incoming data or telecom port and an outgoing data or telecom port of the data switch. The interconnecting switching nodes can achieve high capacity data switching by providing a partial switching solution at each node, distributing the switching load. A switching protocol for interconnecting switching nodes allows data packets to be selectively passed from any incoming port on an interconnecting switch node to any interconnecting switching node or outgoing port connected to it. In at least one example, the switching protocol has mechanisms in it to provide for the duplicating of the contents of the data packet and pass them to multiple interconnecting switching nodes or outgoing ports.
1. A data switching node of a plurality of data switching nodes, the data switching node comprising:
a plurality of data ports; and
a data switch configured for:
receiving a data packet from a first data port of the plurality data ports;
determining a destination address of the data packet;
determining a routing path for the data packet through at least a portion of the plurality of data switching nodes based on the destination address of the data packet;
determining physical addresses of egress ports of the plurality of data switching nodes for the routing path;
modifying a packet header of the data packet to include physical addresses of egress ports; and
transmitting the data packet from a second data port of the plurality of data ports to another data switching node based on at least a portion of the physical addresses of the egress ports.
2. The data switching node of claim 1 , wherein the data packet is an Ethernet datagram.
3. The data switching node of claim 1 , wherein the data packet is an asynchronous transfer mode (ATM) datagram.
4. The data switching node of claim 1 , wherein the another data switching node is configured to modify the packet header of the data packet to remove the physical addresses of the egress ports.
5. The data switching node of claim 1 , wherein the second data port comprises a peripheral component interchange exchange (PCIe) interface.
6. The data switching node of claim 1 , wherein the first data port is configured to receive an aggregate bit rate of approximately 40 Giga-bits-per-second (Gbps) or 100 Gbps.
7. The data switching node of claim 1 , wherein the first data port is configured to receive an aggregate bit rate exceeding 100 Giga-bits-per-second (Gbps).
8. The data switching node of claim 1 , wherein the first data port comprises a telecom physical interface.
9. The data switching node of claim 8 , wherein the first data port is an optical data port.
10. The data switching node of claim 9 , wherein the optical data port is a quad small form-factor pluggable (QSFP) optical port.
11. A method implemented within a data switching node of a plurality of data switching nodes, the method comprising:
a plurality data ports; and
a data switch configured for:
receiving a data packet from a first data port of the plurality data ports implemented within the data switching node;
determining a destination address of the data packet;
determining a routing path for the data packet through at least a portion of the plurality of data switching nodes based on the destination address of the data packet;
determining physical addresses of egress ports of the plurality of data switching nodes for the routing path;
modifying a packet header of the data packet to include physical addresses of egress ports; and
transmitting the data packet from a second data port of the plurality of data ports to another data switching node based on at least a portion of the physical addresses of the egress ports.
12. The method of claim 11 , wherein the data packet is an Ethernet datagram.
13. The method of claim 11 , wherein the data packet is an asynchronous transfer mode (ATM) datagram.
14. The method of claim 11 , wherein the another data switching node is configured to modify the packet header of the data packet to remove the physical addresses of the egress ports.
15. The method of claim 11 , wherein the second data port comprises a peripheral component interchange exchange (PCIe) interface.
16. The method of claim 11 , wherein the first data port is configured to receive an aggregate bit rate of approximately 40 Giga-bits-per-second (Gbps) or 100 Gbps.
17. The method of claim 11 , wherein the first data port is configured to receive an aggregate bit rate exceeding 100 Giga-bits-per-second (Gbps).
18. The method of claim 11 , wherein the first data port comprises a telecom physical interface.
19. The method of claim 18 , wherein the first data port is an optical data port.
20. The method of claim 19 , wherein the optical data port is a quad small form-factor pluggable (QSFP) optical port.