Clock data recovery with decision feedback equalization
Methods and systems are described for generating two comparator outputs by comparing a received signal to a first threshold and a second threshold according to a sampling clock, the first and second thresholds determined by an estimated amount of inter-symbol interference on a multi-wire bus, selecting one of the two comparator outputs as a data decision, the selection based on at least one prior data decision, and selecting one of the two comparator outputs as a phase-error decision, the phase error decision selected in response to identification of a predetermined data decision pattern.
1. A method comprising:
generating two comparator outputs by sampling a data signal at a sampling instant according to a sampling clock and a historical data decision, the two comparator outputs comprising (i) a data decision of the data signal generated using a first decision feedback equalization (DFE) decision threshold and (ii) an edge trajectory sample of the data signal generated using a second DFE decision threshold;
generating a phase-error signal based on the edge trajectory sample and the historical data decision; and
providing the phase-error signal to a clock recovery circuit to adjust the sampling instant of the sampling clock to align the second DFE decision threshold with a trajectory of the data signal at the sampling instant.
2. The method of claim 1 , wherein the phase-error signal is an early/late logic decision determined in response to a transition of the data signal.
3. The method of claim 2 , wherein the transition in the data signal is associated with a predetermined triplet data decision pattern.
4. The method of claim 3 , wherein the predetermined triplet data decision pattern is selected from the group consisting of: [1,0,0] and [0,1,1].
5. The method of claim 1 , further comprising generating the data signal using a sub-channel detection multi-input comparator (MIC) operating on signals received via a plurality of wires.
6. The method of claim 5 , wherein the signals received via the plurality of wires correspond to symbols of a codeword of a vector signaling code, the codeword corresponding to a weighted summation of a plurality of mutually orthogonal sub-channel vectors.
7. The method of claim 6 , wherein each sub-channel comprises sub-channel specific inter-symbol interference (ISI), the sub-channel specific ISI corresponding to modulation of components of a corresponding sub-channel vector associated with the data signal.
8. The method of claim 7 , wherein sub-channel specific ISI associated with each sub-channel vector is mutually orthogonal.
9. The method of claim 1 , further comprising filtering the data signal prior to generating the data decision and edge trajectory sample.
10. The method of claim 9 , wherein the received data signal is low pass filtered.
11. An apparatus comprising:
two comparators collectively configured to generate two comparator outputs by sampling a data signal at a sampling instant according to a sampling clock and a historical data decision, the two comparator outputs comprising (i) a data decision of the data signal generated using a first decision feedback equalization (DFE) decision threshold and (ii) an edge trajectory sample of the data signal generated using a second DFE decision threshold;
a phase-error selection circuit configured to generate a phase-error signal based on the edge trajectory sample and the historical data decision; and
a clock recovery circuit configured to receive the phase-error signal and to responsively adjust the sampling instant of the sampling clock to align the second DFE decision threshold with a trajectory of the data signal at the sampling instant.
12. The apparatus of claim 11 , wherein the phase-error signal is an early/late logic decision determined in response to a transition in the data signal.
13. The apparatus of claim 12 , wherein the transition in the data signal is associated with a predetermined triplet data decision pattern.
14. The apparatus of claim 11 , further comprising a decision-feedback equalization (DFE) circuit configured to generate the first and second DFE decision thresholds.
15. The apparatus of claim 11 , further comprising a sub-channel detection multi-input comparator (MIC) operating on signals received via a plurality of wires of a multi-wire bus, the sub-channel detection MIC configured to generate the data signal.
16. The apparatus of claim 15 , wherein the signals received via the plurality of wires correspond to symbols of a codeword of a vector signaling code, the codeword corresponding to a weighted summation of a plurality of mutually orthogonal sub-channel vectors.
17. The apparatus of claim 16 , wherein the first and second decision thresholds are associated with inter-symbol interference (ISI) on the multi-wire bus.
18. The apparatus of claim 17 , wherein the ISI is sub-channel specific, the sub-channel specific ISI corresponding to modulation of components of a corresponding sub-channel vector associated with the data signal.
19. The apparatus of claim 18 , wherein sub-channel specific ISI associated with each sub-channel vector is mutually orthogonal.
20. The apparatus of claim 11 , further comprising a filter configured to filter the data signal prior to generating the two comparator outputs.