Package structure and method for fabricating the same

1. A package structure, comprising:

a substrate layer comprising a first carrier and a second carrier laterally separated from the first carrier;

a first dielectric layer disposed over the substrate layer;

a first capacitor at least partially disposed in the first dielectric layer, wherein the first capacitor is disposed over the first carrier at a first carrier-side of the first dielectric layer;

a System on Chip unit disposed in the first dielectric layer and over the second carrier at a second carrier-side of the first dielectric layer, wherein the System on Chip unit is separated from the first capacitor by a portion of the first dielectric layer between the System on Chip unit and the first capacitor;

a second dielectric layer disposed over the first dielectric layer; and

a wiring layer disposed in the second dielectric layer and electrically coupling the first capacitor and the System on Chip unit, wherein the wiring layer extends over the first capacitor, wherein the wiring layer further extends over the portion of the first dielectric layer between the System on Chip unit and the first capacitor, and wherein the wiring layer further extends over the System on Chip unit.

2. The package structure of claim 1 , wherein the first capacitor comprises:

a first conductive element formed in the first dielectric layer;

an dielectric element formed on the first conductive element; and

a second conductive element formed on the dielectric element.

3. The package structure of claim 2 , wherein a material of the dielectric element is different from a material of the first dielectric layer and a material of the second dielectric layer.

4. The package structure of claim 1 , wherein the first capacitor comprises:

a first conductive element disposed in the first dielectric layer; and

a second conductive element spaced apart from the first conductive element by a distance.

5. The package structure of claim 1 , further comprising:

a first conductor disposed in the first dielectric layer, the first capacitor electrically coupled to the System on Chip unit through the first conductor and the wiring layer.

6. The package structure of claim 1 , wherein the System on Chip unit comprises a gate driving circuit, and the first capacitor is a bootstrap capacitor of the gate driving circuit.

7. The package structure of claim 1 , wherein the System on Chip unit comprises a GaN power transistor.

8. The package structure of claim 1 , further comprising:

a second capacitor formed in the second dielectric layer and electrically coupled the first capacitor in parallel.

9. A package structure, comprising:

a first dielectric layer disposed over a first carrier and a second carrier laterally separated from the first carrier;

a first conductive element disposed in the first dielectric layer and over the first carrier at a first carrier-side of a first dielectric layer;

a System on Chip unit disposed in the first dielectric layer and over the second carrier at a second carrier-side of the first dielectric layer, wherein the System on Chip unit is separated from the first conductive element by a portion of the first dielectric layer between the System on Chip unit and the first conductive element;

a dielectric element disposed in the first dielectric layer and over the first conductive element at the first carrier-side of the first dielectric layer, wherein the System on Chip unit is separated from the dielectric element by a portion of the first dielectric layer between the System on Chip unit and the dielectric element; and

a second conductive element disposed over the dielectric element, wherein the first conductive element, the dielectric element and the second conductive element form a first capacitor, and wherein the first capacitor and the System on Chip unit are electrically coupled by a wiring layer extending over the first dielectric layer.

10. The package structure of claim 9 , wherein the first conductive element, the second conductive element, the dielectric element and the System on Chip unit are bonded through the first dielectric layer, and the second conductive element is electrically coupled to the System on Chip unit through the wiring layer.

11. The package structure of claim 9 , wherein the second conductive element and the wiring layer are bonded through a second dielectric layer, and the second conductive element is electrically coupled to the System on Chip unit through the wiring layer.

12. The package structure of claim 9 , wherein a material of the dielectric element comprises ceramic or mica.

13. The package structure of claim 9 , wherein a material of the dielectric element is the same as a material of the first dielectric layer.