Data transmission method and apparatus
A disclosure of the present specification provides a method for transmitting data by a transmitter. The method may comprise the steps of: when a transport block (TB) is divided into n data blocks, adding additional information after each of the n data blocks; and adding a cyclic redundancy check (CRC) after the last additional information. Here, the CRC may be generated on the basis of the n data blocks, and the n pieces of additional information added after each of data blocks.
1. A method of transmitting data at a transmitter, the method comprising:
generating an information sequence based on the data;
encoding the information sequence; and
transmitting the encoded information sequence,
wherein the information sequence includes data blocks 0 to N−1 related to the data and parity blocks 0 to N−1 in the order of data block 0 , parity block 0 , data block 1 , parity block 1 , . . . , data block N−1, parity block N−1, where N is an integer larger than 1,
wherein each parity block n of the parity blocks 0 to N−1 is generated based on bits included in data blocks 0 to n−1 and bits included in data block n only, among the data blocks 0 to N−1, and
wherein each parity block n of the parity blocks 0 to N−1 includes at least one cyclic redundancy check (CRC) bit.
2. The method according to claim 1 ,
wherein the information sequence further includes a cyclic redundancy check (CRC) block at an end of the information sequence.
3. The method according to claim 1 ,
wherein each parity block n of the parity blocks 0 to N−1 includes no parity bit which is generated based on parity blocks 0 to n−1, parity blocks n+1 to N−1, and data blocks n+1 to N−1.
4. The method according to claim 1 ,
wherein the encoded information sequence is transmitted through a physical control channel.
5. A transmitter for transmitting data, the transmitter comprising:
a transceiver;
at least one processor; and
at least one computer memory operably connectable to the at least one processor and storing instructions that, when executed by the at least one processor, perform operations comprising:
generating an information sequence based on the data;
encoding the information sequence; and
transmitting, through the transceiver, the encoded information sequence,
wherein the information sequence includes data blocks 0 to N−1 related to the data and parity blocks 0 to N−1 in the order of data block 0 , parity block 0 , data block 1 , parity block 1 , . . . , data block N−1, parity block N−1, where N is an integer larger than 1, and
wherein each parity block n of the parity blocks 0 to N−1 is generated based on bits included in data blocks 0 to n−1 and bits included in data block n only, among the data blocks 0 to N−1, and
wherein each parity block n of the parity blocks 0 to N−1 includes at least one cyclic redundancy check (CRC) bit.
6. The transmitter according to claim 5 ,
wherein the information sequence further includes a cyclic redundancy check (CRC) block at an end of the information sequence.
7. The transmitter according to claim 5 ,
wherein each parity block n of the parity blocks 0 to N−1 includes no parity bit which is generated based on parity blocks 0 to n−1, parity blocks n+1 to N−1, and data blocks n+1 to N−1.
8. The transmitter according to claim 5 ,
wherein the encoded information sequence is transmitted through a physical control channel.
9. A receiver configured to receive data, the receiver comprising:
a transceiver;
at least one processor; and
at least one computer memory operably connectable to the at least one processor and storing instructions that, when executed by the at least one processor, perform operations comprising:
receiving, through the transceiver, an encoded information sequence related to the data; and
performing decoding on the encoded information sequence to obtain an information sequence,
wherein the information sequence includes data blocks 0 to N−1 related to the data and parity blocks 0 to N−1 in the order of data block 0 , parity block 0 , data block 1 , parity block 1 , . . . , data block N−1, parity block N−1, where N is an integer larger than 1,
wherein each parity block n of the parity blocks 0 to N−1 is related to bits included in data blocks 0 to n−1 and bits included in data block n only, among the data blocks 0 to N−1, and
wherein each parity block n of the parity blocks 0 to N−1 includes at least one cyclic redundancy check (CRC) bit.
10. The receiver according to claim 9 ,
wherein the information sequence further includes a cyclic redundancy check (CRC) block at an end of the information sequence.
11. The receiver according to claim 9 ,
wherein each parity block n of the parity blocks 0 to N−1 includes no parity bit which is related to parity blocks 0 to n−1, parity blocks n+1 to N−1, and data blocks n+1 to N−1.
12. The receiver according to claim 9 ,
wherein the encoded information sequence is received through a physical control channel.