Buffering device with status communication method for memory controller
In an example, the present invention provides a memory interface device. The device has a command interface, address interface, and a control interface device coupled, respectively, to a command address bus, an address bus, and a control interface bus of a host memory controller. The device has a status signal interface configured to output a status signal coupled to the data interface bus of the host memory controller. In an example, the status signal is asserted in an absence of data asserted on the data interface bus.
1. A memory interface device comprising:
an interface to couple to a host memory controller and to one or more memory devices, wherein the interface is configured to receive a read access command from the host memory controller, the read access command comprising an address of data to be read from the one or more memory devices, and to send address information corresponding to the address to the one or more memory devices; and
a status generator circuit coupled to the interface and to couple to the host memory controller, wherein the status generator circuit is configured to:
detect a status of the read access command;
generate a status signal to reflect the status of the read access command, wherein the status signal comprises an indication of a reason why the read access command was not completed within a predetermined latency period; and
send the status signal to the host memory controller.
2. The memory interface device of claim 1 , wherein interface is further configured to:
receive the data from the one or more memory devices; and
send the data to the host memory controller.
3. The memory interface device of claim 1 , wherein the interface to couple to the host memory controller via a first command bus, a first address bus and a first data bus, and to couple to the one or more memory devices via a second command bus, a second address bus and a second data bus.
4. The memory interface device of claim 1 , wherein the status generator circuit is configured to send the status signal to the host memory controller via the first data bus.
5. The memory interface device of claim 1 , wherein if the interface receives the data from the one or more memory devices within the predetermined latency period, the status generator circuit is configured to:
determine a first status; and
de-assert the status signal.
6. The memory interface device of claim 5 , wherein if the interface does not receive the data from the one or more memory devices within the predetermined latency period, the status generator circuit is configured to:
determine a second status; and
assert the status signal.
7. The memory interface device of claim 6 , wherein the status signal comprises an indication of a time when the read access command can be retried.
8. A method of operating a memory interface device, the method comprising:
receiving, by an interface of the memory interface device, a read access command from a host memory controller, the read access command comprising an address of data to be read from one or more memory devices;
sending, by the interface, address information corresponding to the address to the one or more memory devices to the one or more memory devices bus;
detecting, by a status generator circuit of the memory interface device, a status of the read access command;
generating, by the status generator circuit, a status signal to reflect the status of the read access command, wherein the status signal comprises an indication of a reason why the read access command was not completed within a predetermined latency period; and
sending, by the status generator circuit, the status signal to the host memory controller.
9. The method of claim 8 , further comprising:
receiving, by the interface, the data from the one or more memory devices; and
sending, by the interface, the data to the host memory controller.
10. The method of claim 8 , wherein the interface to couple to the host memory controller via a first command bus, a first address bus and a first data bus, and to couple to the one or more memory devices via a second command bus, a second address bus and a second data bus.
11. The method of claim 10 , wherein sending the status signal to the host memory controller comprises asserting the status signal on the first data bus.
12. The method device of claim 8 , wherein if the interface receives the data from the one or more memory devices within the predetermined latency period, the method further comprising:
determining, by the status generator circuit, a first status; and
de-asserting, by the status generator circuit, the status signal.
13. The method device of claim 12 , wherein if the interface does not receive the data from the one or more memory devices within the predetermined latency period, the method further comprising:
determining, by the status generator circuit, a second status; and
asserting, by the status generator circuit, the status signal on a status bus coupled between the memory interface device and the host memory controller.
14. The method device of claim 13 , wherein the status signal comprises an indication of a time when the read access command can be retried.
15. A memory interface device comprising:
an interface to couple to a host memory controller and to one or more memory devices, wherein the interface is configured to receive a read access command from the host memory controller, the read access command comprising an address of data to be read from the one or more memory devices, and to send address information corresponding to the address to the one or more memory devices; and
a status generator circuit coupled to the interface and to couple to the host memory controller, wherein the status generator circuit is configured to:
determine whether the read access command is completed within a predetermined latency period; and
if the read access command is not completed within the predetermined latency period, send a status signal to the host memory controller indicating that the read access command is delayed, wherein the status signal comprises an indication of a reason why the read access command was delayed.
16. The memory interface device of claim 15 , wherein interface is further configured to:
receive the data from the one or more memory devices; and
send the data to the host memory controller.
17. The memory interface device of claim 15 , wherein the interface to couple to the host memory controller via a first command bus, a first address bus and a first data bus, and to couple to the one or more memory devices via a second command bus, a second address bus and a second data bus.
18. The memory interface device of claim 17 , wherein the status generator circuit is configured to send the status signal to the host memory controller via the first data bus.
19. The memory interface device of claim 15 , wherein the status generator circuit is further configured to:
if the read access command is completed within the predetermined latency period, de-assert the status signal.
20. The memory interface device of claim 15 , wherein the status signal comprises an indication of a time when the read access command can be retried.