Method to form memory cells separated by a void-free dielectric structure

1. An integrated chip comprising:

a pair of wires;

a first memory cell structure and a second memory cell structure over the wires;

an inter-cell filler layer separating the first and second memory cell structures and having a top surface recessed below a top surface of the first memory cell structure, wherein the inter-cell filler layer is on a first side of the first memory cell structure facing the second memory cell structure, but is not on a second side of the first memory cell structure opposite the first side; and

an interconnect dielectric layer overlying the first and second memory cell structures and the inter-cell filler layer, and further extending towards the top surface of the inter-cell filler layer to below the top surface of the first memory cell structure.

2. The integrated chip according to claim 1 , wherein the top surface of the inter-cell filler layer arcs continuously from proximate the first memory cell structure to proximate the second memory cell structure.

3. The integrated chip according to claim 1 , further comprising:

an array of memory cell structures, wherein the array comprises the first and second memory cell structures, and wherein the inter-cell filler layer has a top layout that is grid shaped and terminates at edges of the array.

4. The integrated chip according to claim 1 , further comprising:

a conductive line overlying the first memory cell structure and sunken into the interconnect dielectric layer; and

a via within the interconnect dielectric layer and extending from the conductive line to the first memory cell structure.

5. The integrated chip according to claim 4 , wherein the conductive line overlies the second memory cell structure, and wherein the conductive line has a downward protrusion laterally between the first and second memory cell structures.

6. The integrated chip according to claim 1 , wherein the inter-cell filler layer comprises tetraethyl orthosilicate (TEOS) oxide, and wherein the interconnect dielectric layer comprises a dielectric material having a dielectric constant less than about 2.0.

7. The integrated chip according to claim 1 , wherein the first and second memory cell structures have a height and are separated by a separation amount, wherein a ratio of the height to the separation amount is greater than about 2.5:1, and wherein the inter-cell filler layer and the interconnect dielectric layer are free of voids laterally between the first and second memory cell structures.

8. An integrated chip comprising:

a pair of wires;

a first memory cell structure and a second memory cell structure overlying the wires;

an inter-cell filler layer overlying the first and second memory cell structures and filling an inter-cell area directly between the first and second memory cell structures, wherein the inter-cell filler layer has a greater thickness at the inter-cell area than atop the first and second memory cell structures;

an interconnect dielectric layer overlying the inter-cell filler layer, wherein the interconnect dielectric layer has a dielectric constant less than that of the inter-cell filler layer;

a conductive line inset into the interconnect dielectric layer; and

a via extending from the conductive line, through the inter-cell filler layer, to the first memory cell structure.

9. The integrated chip according to claim 8 , wherein the conductive line overlies the second memory cell structure, and wherein the inter-cell filler layer has a top surface that is indented laterally between the first and second memory cell structures.

10. The integrated chip according to claim 8 , wherein the conductive line overlies the second memory cell structure, and wherein the inter-cell filler layer has a top surface that is substantially planar from directly over the first memory cell structure to directly over the second memory cell structure.

11. The integrated chip according to claim 8 , wherein a top surface of the via is elevated above a top surface of the inter-cell filler layer.

12. The integrated chip according to claim 8 , wherein the inter-cell filler layer comprises tetraethyl orthosilicate (TEOS) oxide, and wherein the interconnect dielectric layer comprises a dielectric material having a dielectric constant less than about 2.5.

13. An integrated chip comprising:

a lower wire;

a via dielectric layer overlying the lower wire;

a first memory cell and a second memory cell overlying the via dielectric layer and bordering, wherein the first memory cell comprises a data storage layer;

a lower via extending from the first memory cell to the lower wire;

a gap-fill dielectric layer laterally separating the first and second memory cells, wherein a height of the gap-fill dielectric layer extends vertically from a first elevation to a second elevation at a center between the first and second memory cells;

an interconnect dielectric layer overlying the first and second memory cells and the gap-fill dielectric layer, wherein the interconnect dielectric layer has a low dielectric constant relative to the gap-fill dielectric layer;

an upper wire inset into a top surface of the interconnect dielectric layer and having a bottom surface elevated above a top surface of the gap-fill dielectric layer; and

an upper via extending from the upper wire to the first memory cell;

wherein the data storage layer has a sidewall facing the gap-fill dielectric layer, and wherein the first and second elevations are respectively above a top edge of the sidewall and below a bottom edge of the sidewall.

14. The integrated chip according to claim 13 , wherein the top surface of the gap-fill dielectric layer is completely recessed relative to a top surface of the first memory cell.

15. The integrated chip according to claim 13 , wherein the gap-fill dielectric layer overlies the first and second memory cells, and wherein the upper via laterally and directly contacts both the interconnect dielectric layer and the gap-fill dielectric layer.

16. The integrated chip according to claim 15 , wherein the top surface of the gap-fill dielectric layer is substantially planar.

17. The integrated chip according to claim 13 , wherein the gap-fill dielectric layer has a first sidewall and a second sidewall respectively bordering the first and second memory cells, and wherein the height increases continuously from the center to a bottom edge of each of the first and second sidewalls.

18. The integrated chip according to claim 17 , wherein the height decreases continuously from the bottom edge of the first sidewall to a top edge of the first sidewall.

19. The integrated chip according to claim 13 , wherein the gap-fill dielectric layer has a first sidewall and a second sidewall respectively bordering the first and second memory cells, and wherein the height is uniform from the center to a bottom edge of each of the first and second sidewalls.

20. The integrated chip according to claim 13 , further comprising:

an array of memory cells overlying the via dielectric layer, wherein the array includes the first and second memory cells bordering in a row of the array, wherein the array further includes a third memory cell bordering the first memory cell in a column of the array, wherein the gap-fill dielectric layer has a first dimension along the row and directly between the first and second memory cells, wherein the gap-fill dielectric layer has a second dimension along the column and directly between the first and third memory cells, and wherein the second dimension is greater than the first dimension.