IP Library Granted Patent US 10,560,027
Granted Patent B2
US 10,560,027 · App. 16/266,814 · Granted Feb 11, 2020

Semiconductor device and method therefor

Inventors: Zhibo Tao (Palo Alto, CA); Chih-Hsien Hsieh (Changhua County, TW); Yue-Hong Tang (Nantou County, TW)
Assignee: FAIRCHILD SEMICONDUCTOR CORPORATION
H02M3/33515H02M1/08H02M3/33592H02M3/33523H02M2001/0009Y02B70/1475
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Quick Facts
Patent No.
US 10,560,027
App. No.
16/266,814
Granted
Feb 11, 2020
Kind
B2
Abstract

In one embodiment, a power supply controller, or alternately a semiconductor device having a power supply controller, may have a first circuit configured to form a sense signal that is representative of a signal from an auxiliary winding of a transformer. A feedback circuit may be configured to allow the sense signal to increase in response to a turn-off of the power switch, to subsequently detect a second increase of the sense signal prior to subsequently turning on the power switch, and to form a feedback signal as a value of the sense signal responsively to the second increase of the sense signal.

Claims (30)

1. A power supply circuit having a control circuit comprising:

configuring a PWM circuit of the control circuit to control a power switch to regulate an output voltage formed from a secondary winding of a transformer wherein the secondary winding is configured to be coupled to a synchronous rectifier;

a feedback circuit configured to receive a sense signal from an auxiliary winding of the transformer, the feedback circuit configured to allow the sense signal to increase in response to a turn-off of the power switch, to subsequently detect a second increase of the sense signal that occurs in response to a turn-off of the synchronous rectifier, and to form a feedback signal as a value of the sense signal responsively to detecting the second increase of the sense signal; and

the control circuit configured to adjust an on-time of a subsequent enabling of the power switch according to a value of the feedback signal.

2. The power supply circuit of claim 1 wherein the feedback circuit includes a sampling circuit configured to store a first value of the sense signal responsively to detecting the second increase of the sense signal.

3. The power supply circuit of claim 2 further including a first detection circuit configured to store a value of the sense signal responsively to disabling the power switch and to detect the sense signal having a value greater than a stored value for detecting the second increase of the sense signal.

4. The power supply circuit of claim 3 wherein the first detection circuit includes a first switch configured to couple the sense signal to a capacitor in order to store the value of the sense signal.

5. The power supply circuit of claim 3 wherein the first detection circuit adds an offset value to the stored value to form an offset sense signal.

6. The power supply circuit of claim 5 wherein the first detection circuit includes a comparator to compare the sense signal to the offset sense signal.

7. The power supply circuit of claim 2 wherein the sampling circuit is also configured to store the first value of the sense signal responsively to detecting a decrease of the sense signal.

8. The power supply circuit of claim 7 wherein the sampling circuit includes a detection circuit having a delay circuit that receives the sense signal and forms a delayed signal, and a comparator that compares the delayed signal to an offset value of the sense signal.

9. A method of forming a power supply controller comprising:

configuring a first circuit to control a power switch to regulate an output voltage formed from a secondary winding of a transformer wherein the secondary winding is configured to be coupled to a synchronous rectifier;

configuring a second circuit to receive a sense signal from an auxiliary winding of the transformer;

configuring a third circuit to store a value of the sense signal as a feedback signal responsively to detecting the synchronous rectifier turning off prior to a secondary current through the synchronous rectifier becoming substantially zero; and

configuring the first circuit to adjust an on-time of a subsequent enabling of the power switch according to a value of the sense signal.

10. The method of claim 9 including configuring the third circuit to store the value of the sense signal as the feedback signal responsively to detecting the sense signal increasing from a first value to a second value wherein the second value occurs responsively to disabling the synchronous rectifier.

11. The method of claim 10 including configuring the third circuit to allow the sense signal to increase in response to disabling the power switch to form the first value and to subsequently detect the sense signal increasing to the second value.

12. The method of claim 10 including configuring the third circuit to sample the sense signal for a first time interval responsively to disabling the power switch to form a sampled value and subsequently detect the sense signal increasing to greater than the sampled value.

13. The method of claim 12 including configuring the third circuit to store the sense signal on a capacitor for the first time interval to form a stored value, to add an offset to the stored value to form an offset value, and to compare the offset value to the sense signal.

14. The method of claim 9 including configuring the third circuit to store the sense signal as the feedback signal responsively to detecting a decrease of the sense signal subsequently to disabling the power switch.

15. A method of forming a power supply circuit comprising:

configuring a PWM circuit to control a power switch to regulate an output voltage formed from a secondary winding of a transformer wherein the secondary winding is configured to be coupled to a synchronous rectifier;

configuring a feedback circuit to receive a sense signal from an auxiliary winding of the transformer and to detect a turn-off of the synchronous rectifier; and

configuring the feedback circuit to form a feedback signal as a value of the sense signal responsively to detecting the turn-off of the synchronous rectifier.

16. The method of claim 15 including configuring the PWM circuit to adjust an on-time of a subsequent enabling of the power switch according to a value of the feedback signal.

17. The method of claim 15 including configuring the feedback circuit to form the feedback signal as a value of the sense signal responsively to detecting a substantially zero crossing of a secondary current from the secondary winding.

18. The method of claim 17 further including configuring a detection circuit to receive the sense signal and delay the sense signal to form a delayed signal, and configuring the detection circuit to compare the delayed signal to the sense signal added to an offset signal.

19. The method of claim 15 wherein configuring the feedback circuit to detect the turn-off of the synchronous rectifier includes configuring a detection circuit to detect the synchronous rectifier turning-off prior to a substantially zero value of a current through the synchronous rectifier.

20. The method of claim 19 including configuring the feedback circuit to delay a time interval after disabling the power switch and subsequently detect an increase of the sense signal for detecting the turn-off of the synchronous rectifier.

Assignments (7)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 058871, FRAME 0799 Recorded Jun 23, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 065653/0001 →
SECURITY INTEREST Recorded Nov 12, 2021
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 058871/0799 →
RELEASE OF SECURITY INTEREST Recorded Oct 28, 2021
From: DEUTSCHE BANK AG NEW YORK BRANCH
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 057969/0206 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 3, 2021
From: FAIRCHILD SEMICONDUCTOR CORPORATION
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 057694/0374 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 4, 2019
From: TAO, ZHIBO; HSIEH, CHIH-HSIEN; TANG, YUE-HONG
To: FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 049091/0408 →
Continuity (3)
Continuation 15472802 · Mar 29, 2017
Provisional Application 62324517 · Apr 19, 2016
Related Publication 20190181763A1 · Jun 13, 2019