Systems and methods for addressing a cache with split-indexes
Cache memory mapping techniques are presented. A cache may contain an index configuration register. The register may configure the locations of an upper index portion and a lower index portion of a memory address. The portions may be combined to create a combined index. The configurable split-index addressing structure may be used, among other applications, to reduce the rate of cache conflicts occurring between multiple processors decoding the video frame in parallel.
1. A processor subsystem comprising:
one or more processor cores, the one or more processor cores to communicate with a memory; and
a cache including a plurality of cache lines, the cache to:
determine a first index from a first set of bits of a first address associated with a first location of the memory;
determine a second index from a second set of bits of the first address, the second set of bits of the first address separated from the first set of bits of the first address by a third set of bits of the first address; and
store data from the first location of the memory in a first one of the cache lines referenced by a combined index, the combined index based on a combination of the first index and the second index.
2. The processor subsystem of claim 1 , wherein the cache is to concatenate the first index and the second index to determine the combined index.
3. The processor subsystem of claim 1 , wherein the cache is further to combine the third set of bits of the first address and a fourth set of bits of the first address to determine an identifier to identify the first location of the memory.
4. The processor subsystem of claim 3 , wherein the cache is to concatenate the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.
5. The processor subsystem of claim 3 , wherein the cache is to determine a position within the first one of the cache lines to which the first location of the memory is mapped, the cache to determine the position based on a fifth set of bits of the first address.
6. The processor subsystem of claim 1 , wherein at least one of the first set of bits of the first address, the second set of bits of the first address, or the third set of bits of the first address has a size of one bit.
7. The processor subsystem of claim 1 , wherein the one or more processor cores include at least two processor cores, and respective ones of the at least two processor cores are to access different ones of the cache lines simultaneously.
8. An apparatus comprising:
cache lines referenced by indexes;
means for determining a first index portion and a second index portion from respective first and second sets of bits of a first address associated with a first location of memory, the first and second sets of bits of the first address separated by a third set of bits of the first address; and
means for mapping the first location of the memory to a first one of the cache lines referenced by a first one of the indexes, the means for mapping to determine the first one of the indexes based on a combination of the first index portion and the second index portion, the cache to store data from the first location of the memory in the first one of the cache lines.
9. The apparatus of claim 8 , wherein the means for mapping is to concatenate the first index portion and the second index portion to determine the first one of the indexes.
10. The apparatus of claim 8 , wherein the means for determining is to combine the third set of bits of the first address and a fourth set of bits of the first address to determine an identifier to identify the first location of the memory.
11. The apparatus of claim 10 , wherein the means for determining is to concatenate the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.
12. The apparatus of claim 10 , wherein the means for determining is to determine a position within the first one of the cache lines to which the first location of the memory is mapped, the position to be determined based on a fifth set of bits of the first address.
13. The apparatus of claim 8 , wherein at least one of the first set of bits of the first address, the second set of bits of the first address, or the third set of bits of the first address has a size of one bit.
14. The apparatus of claim 8 , further including means for scheduling at least two processor cores to access different ones of the cache lines simultaneously.
15. A method comprising:
determining, with a logic circuit, a first index from a first set of bits of a first address associated with a first location of memory;
determining, with the logic circuit, a second index from a second set of bits of the first address, the second set of bits of the first address separated from the first set of bits of the first address by a third set of bits of the first address; and
storing data from the first location of the memory in a first one of a plurality of cache lines referenced by a combined index, the combined index based on a combination of the first index and the second index.
16. The method of claim 15 , further including concatenating the first index and the second index to determine the combined index.
17. The method of claim 15 , further including combining the third set of bits of the first address and a fourth set of bits of the first address to determine an identifier to identify the first location of the memory.
18. The method of claim 17 , wherein the combining of the third set of bits of the first address and the fourth set of bits of the first address includes concatenating the third set of bits of the first address and the fourth set of bits of the first address to determine the identifier.
19. The method of claim 17 , further including determining a position within the first one of the cache lines to which the first location of the memory is mapped, the determining of the position based on a fifth set of bits of the first address.
20. The method of claim 15 , wherein at least one of the first set of bits of the first address, the second set of bits of the first address, or the third set of bits of the first address has a size of one bit.