Resistive memory with a plurality of resistive random access memory cells each comprising a transistor and a resistive element
A method of forming a semiconductor structure includes forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate and forming a plurality of resistive elements disposed over top surfaces of the VFETs. Each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell. The VFETs are arranged in two or more columns and two or more rows, wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region and wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate. Top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs.
1. A method of forming a semiconductor structure, comprising:
forming a plurality of vertical field-effect transistors (VFETs) disposed on a substrate; and
forming a plurality of resistive elements disposed over top surfaces of the VFETs;
wherein each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell;
wherein the VFETs are arranged in two or more columns and two or more rows;
wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;
wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;
wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs; and
wherein the plurality of VFETs comprise a plurality of fins disposed over the substrate, and further comprising forming a plurality of pillars disposed over each of the plurality of fins, each pillar comprising a channel and one of the top source/drain regions disposed over the channel.
2. The method of claim 1 , wherein each of the plurality of fins comprising a doped layer disposed over the substrate providing the bottom source/drain regions for a respective bitline of the ReRAM cells.
3. The method of claim 1 , further comprising forming top spacers for each of the plurality of pillars.
4. The method of claim 3 , wherein forming the plurality of resistive elements comprises:
forming bottom electrodes disposed over top surfaces of the top source/drain regions;
forming switch material disposed over top surfaces of the bottom electrodes and on portions of sidewalls of top spacers of each of the pillars; and
forming top electrodes disposed over the switch material.
5. The method of claim 4 , wherein the bottom electrodes comprise nitrogen-rich titanium nitride (TiN), the switch material comprises hafnium oxide (HfO X ), and the top electrodes comprise titanium-rich TiN.
6. The method of claim 5 , wherein forming the plurality of resistive elements further comprises forming top contacts disposed over top surfaces of the top electrodes.
7. A semiconductor structure, comprising:
a plurality of vertical field-effect transistors (VFETs) disposed on a substrate; and
a plurality of resistive elements disposed over top surfaces of the VFETs;
wherein each pair of a given one of the plurality of VFETs and a corresponding resistive element disposed over the given VFET provides a resistive random access memory (ReRAM) cell;
wherein the VFETs are arranged in two or more columns and two or more rows;
wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;
wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;
wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs; and
wherein the plurality of VFETs comprise a plurality of fins disposed over the substrate, and further comprising a plurality of pillars disposed over each of the plurality of fins, each pillar comprising a channel and one of the top source/drain regions disposed over the channel.
8. The semiconductor structure of claim 7 , wherein each of the plurality of fins comprising a doped layer disposed over the substrate providing the bottom source/drain regions for a respective bitline of the ReRAM cells.
9. The semiconductor structure of claim 7 , further comprising top spacers for each of the plurality of pillars.
10. The semiconductor structure of claim 9 , wherein the plurality of resistive elements comprise:
bottom electrodes disposed over top surfaces of the top source/drain regions;
switch material disposed over top surfaces of the bottom electrodes and on portions of sidewalls of top spacers of each of the pillars; and
top electrodes disposed over the switch material.
11. The semiconductor structure of claim 10 , wherein the bottom electrodes comprise nitrogen-rich titanium nitride (TiN), the switch material comprises hafnium oxide (HfO X ), and the top electrodes comprise titanium-rich TiN.
12. The semiconductor structure of claim 11 , wherein the plurality of resistive elements further comprises top contacts disposed over top surfaces of the top electrodes.
13. An integrated circuit comprising:
a resistive random access memory (ReRAM) device comprising a plurality of ReRAM cells, each of the plurality of ReRAM cells comprising:
a given one of a plurality of vertical field-effect transistors (VFETs) disposed on a substrate; and
a given one of a plurality of resistive elements disposed over a top surface of the given VFET;
wherein the VFETs are arranged in two or more columns and two or more rows;
wherein each column of VFETs provides a bitline of the ReRAM cells sharing a bottom source/drain region;
wherein each row of VFETs provides a wordline of the ReRAM cells sharing a gate;
wherein top source/drain regions of the VFETs provide bottom contacts for the resistive elements disposed over the VFETs; and
wherein the plurality of VFETs comprise a plurality of fins disposed over the substrate, and further comprising a plurality of pillars disposed over each of the plurality of fins, each pillar comprising a channel and one of the top source/drain regions disposed over the channel.
14. The integrated circuit of claim 13 , wherein each of the plurality of fins comprising a doped layer disposed over the substrate providing the bottom source/drain regions for a respective bitline of the ReRAM cells.
15. The integrated circuit of claim 13 , further comprising top spacers for each of the plurality of pillars.
16. The integrated circuit of claim 15 , wherein the plurality of resistive elements comprise:
bottom electrodes disposed over top surfaces of the top source/drain regions;
switch material disposed over top surfaces of the bottom electrodes and on portions of sidewalls of top spacers of each of the pillars; and
top electrodes disposed over the switch material.
17. The integrated circuit of claim 16 , wherein the bottom electrodes comprise nitrogen-rich titanium nitride (TiN), the switch material comprises hafnium oxide (HfO X ), and the top electrodes comprise titanium-rich TiN.