Superjunction semiconductor device and method of manufacturing the same
In at least one general aspect, a method can include forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region, and forming a second semiconductor layer on the first semiconductor layer. The method can include forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer, and annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.
1. A method, comprising:
forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region;
forming a second semiconductor layer on the first semiconductor layer; and
forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer,
the plurality of first active pillars and the plurality of second active pillars having impurities diffused such that the plurality of first active pillars and the plurality of second active pillars are connected.
2. The method of claim 1 , wherein each of the plurality of preliminary charge balance layers have a width greater than or less than a width of a trench of the plurality of second active pillars.
3. The method of claim 1 , wherein the plurality of preliminary charge balance layers have widths that decrease with distance from the plurality of second active pillars.
4. The method of claim 1 , further comprising:
forming a third second semiconductor layer on the second semiconductor layer, the third semiconductor layer having a thickness less than a thickness of the second semiconductor layer.
5. The method of claim 1 , wherein the plurality of edge pillars are formed via a plurality of edge openings regularly arranged in a matrix form.
6. The method of claim 5 , wherein the plurality of edge openings have a circular shape.
7. The method of claim 1 , wherein at least one of the plurality of edge pillars is formed via an edge opening and at least one of the plurality of first active pillars is formed via an active trench opening, the active trench opening has an area the same as an area of the edge opening.
8. The method of claim 1 , wherein the first semiconductor layer is an epitaxial layer that has a thickness the same as the thickness of the second semiconductor layer.
9. The method of claim 1 , wherein the edge pillars are disposed in the termination region and the first active pillars are disposed in the active region.
10. The method of claim 1 , further comprising:
annealing the first and second semiconductor layers,
during the annealing, impurities implanted into the plurality of preliminary charge balance layers being diffused, and adjacent layers of the plurality of preliminary charge balance layers being connected to form a lower charge balance region having a tapered shape or a non-tapered shape.
11. The method of claim 1 , wherein the forming the plurality of first active pillars and the plurality of edge pillars includes respectively implanting impurities in the active region and the termination region of the first semiconductor layer to form the plurality of first active pillars and the plurality of edge pillars.
12. The method of claim 1 , further comprising:
annealing the first and second semiconductor layers such that the plurality of first active pillars and the plurality of second active pillars are connected,
during the annealing, impurities implanted into the plurality of edge pillars and the plurality of preliminary charge balance layers being diffused, and the plurality of edge pillars and the plurality of preliminary charge balance layers being connected.
13. A method, comprising:
forming a plurality of first active pillars and a plurality of edge pillars in a first semiconductor layer including an active region and a termination region;
forming a second semiconductor layer on the first semiconductor layer; and
forming a plurality of second active pillars and a plurality of preliminary charge balance layers in the second semiconductor layer,
the plurality of preliminary charge balance layers being diffused, and adjacent ones of the plurality of preliminary charge balance layers being connected, thereby forming a lower charge balance region.
14. The method of claim 13 , further comprising:
annealing the first and second semiconductor layers,
during the annealing, the plurality of first active pillars and the plurality of second active pillars being connected by diffusing impurities implanted into the plurality of first active pillars and the plurality of second active pillars.
15. The method of claim 13 , wherein the forming the plurality of second active pillars and the plurality of preliminary charge balance layers includes respectively implanting impurities into the active region and the termination region of the second semiconductor layer, using a second ion implantation mask, thereby forming the plurality of second active pillars and the plurality of preliminary charge balance layers, and
the second ion implantation mask includes a plurality of stripe-shaped first trenches extending in a first direction and a plurality of openings spaced apart from each other in the first direction and a second direction perpendicular to the first direction.
16. The method of claim 13 , wherein the forming the plurality of first active pillars and the plurality of edge pillars includes respectively implanting impurities in the active region and the termination region of the first semiconductor layer, using a first ion implantation mask, thereby forming the plurality of first active pillars and the plurality of edge pillars, and
the first ion implantation mask includes a plurality of stripe-shaped second trenches extending in a first direction and a plurality of stripe-shaped third trenches extending in the first direction.
17. The method of claim 13 , wherein the plurality of edge pillars and the plurality of preliminary charge balance layers are connected during an annealing process.
18. The method of claim 13 , further comprising:
annealing the first and second semiconductor layers,
in the annealing, impurities implanted into the plurality of preliminary charge balance layers being diffused, and adjacent ones of the plurality of preliminary charge balance layers being connected, thereby forming a lower charge balance region.
19. The method of claim 13 , wherein each of the plurality of preliminary charge balance layers have a width greater than or less than a width of a trench of the plurality of second active pillars.
20. The method of claim 13 , wherein the plurality of preliminary charge balance layers have widths that decrease with distance from the plurality of second active pillars.
21. A method, comprising:
forming a termination region around an active region,
forming, in the active region, a drift layer disposed on a semiconductor layer having a first conductivity type;
forming, in the termination region, an upper edge region including:
a lower charge balance region disposed on one side of the drift layer, the lower charge balance region having second conductivity type, the lower charge balance region having a tapered shape or a non-tapered shape, and
an upper charge balance region disposed on the lower charge balance region, the upper charge balance region having the first conductivity.
22. The method of claim 21 , further comprising:
forming a transition region disposed between the active region and the termination region.