IP Library Granted Patent US 10,615,722
Granted Patent B2
US 10,615,722 · App. 16/269,677 · Granted Apr 7, 2020

Controlling multiple facets of duty cycle response using a single motor integrated circuit pin

Inventors: Takashi Ogawa (Ogaki, JP); Fumio Kumazawa (Ota, JP)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H02P6/14H02P6/24H02P27/08
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Quick Facts
Patent No.
US 10,615,722
App. No.
16/269,677
Granted
Apr 7, 2020
Kind
B2
Abstract

A system, in some embodiments, includes: a motor; and control logic, coupled to the motor, to determine a duty keep status and a duty cycle threshold based on a received voltage, wherein the duty keep status indicates whether the system is to operate in a duty keep mode or a stop mode, wherein the duty cycle threshold indicates a minimum duty cycle for the motor if the system operates in said duty keep mode and indicates an input duty cycle threshold below which the control logic shuts off the motor if the system operates in the stop mode.

Claims (34)

1. A system for controlling a motor, the system comprising:

a motor driver coupled to an output of a motor integrated circuit (IC), the motor IC comprising:

a control logic configured to receive a voltage signal;

a pulse-width-modulation (PWM) logic coupled with the control logic, the control logic configured to receive a PWM input signal; and

a motor controller coupled to an output of the control logic;

wherein the control logic is configured to generate a keep status and a duty cycle threshold based upon the voltage signal; and

wherein the keep status comprises one of a keep mode or a stop mode.

2. The system of claim 1 , wherein the control logic is configured to send a stop signal if the control logic generates the stop mode and if the PWM input signal is less than the duty cycle threshold.

3. The system of claim 1 , wherein the motor IC receives the voltage signal through a single input pin.

4. The system of claim 1 , wherein the control logic comprises a set of voltage values and a corresponding set of duty cycle threshold values.

5. The system of claim 4 , wherein a plurality of consecutive voltage values correspond to a single duty cycle threshold value.

6. The system of claim 4 , wherein the set of voltage values and the set of duty cycle threshold values comprise a first portion corresponding to the keep mode and a second portion corresponding to the stop mode.

7. The system of claim 6 , wherein the voltage signal corresponds with one of the first portion or the second portion.

8. A motor integrated circuit comprising:

a control logic configured to receive a voltage signal; and

a pulse-width-modulation (PWM) logic coupled to the control logic, the control logic configured to receive a PWM input signal from the PWM logic;

wherein the control logic is configured to generate a keep status and a duty cycle threshold based upon the voltage signal, the keep status comprising one of a stop mode or a keep mode; and

wherein the control logic is configured to send a stop signal to a motor controller if the control logic generates the stop mode and if the PWM input signal is less than the duty cycle threshold.

9. The circuit of claim 8 , wherein the control logic is configured to output a signal to maintain motor rotation if the control logic generates the keep mode.

10. The circuit of claim 8 , wherein the control logic comprises a processor configured to receive the PWM input signal and the voltage signal.

11. The circuit of claim 8 , wherein the circuit comprises the motor controller coupled to the control logic.

12. The circuit of claim 8 , wherein the control logic comprises a set of voltage values and a set of duty cycle threshold values.

13. The system of claim 12 , wherein a plurality of consecutive voltage values correspond to a single duty cycle threshold value.

14. The system of claim 12 , wherein the set of voltage values and the set of duty cycle threshold values comprise a first portion corresponding to the keep mode and a second portion corresponding to the stop mode.

15. The system of claim 14 , wherein the voltage signal corresponds with one of the first portion or the second portion.

16. A method of controlling a motor, the method comprising:

receiving, at a control logic, a voltage signal, the control logic comprising a set of voltage values and a set of duty cycle values;

calculating, using the control logic, a keep status and a duty cycle threshold based on the voltage signal, the set of voltage values, and the set of duty cycle values, wherein the keep status comprises one of a keep mode or a stop mode;

receiving, at the control logic, a pulse-width-modulation (PWM) input signal from a PWM logic; and

sending one of a stop signal or an output signal to a motor controller indicating that a motor is to continue rotating.

17. The method of claim 16 , further comprising converting the voltage signal using an analog-to-digital converter.

18. The method of claim 16 , wherein calculating comprises comparing the voltage signal to the set of voltage values comprised in the control logic.

19. The method of claim 16 , wherein the set of voltage values corresponds to a set of duty cycle thresholds.

20. The method of claim 16 , wherein the keep status and the duty cycle threshold are calculated without using the PWM input signal.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2019
From: OGAWA, TAKASHI; KUMAZAWA, FUMIO
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 048263/0467 →