IP Library › Granted Patent US 10,658,344
Granted Patent B2
US 10,658,344 · App. 16/269,815 · Granted May 19, 2020

Semiconductor device

Inventor: Hiroshi Matsuyama (Hyogo, JP)
Assignees: Kabushiki Kaisha Toshiba; Toshiba Electronic Devices & Storage Corporation
H01L25/072H01L23/49811H01L23/49844H01L23/5386
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Quick Facts
Patent No.
US 10,658,344
App. No.
16/269,815
Granted
May 19, 2020
Kind
B2
Abstract

A semiconductor device of an embodiment includes a metal layer; a semiconductor chip on the metal layer and having an upper electrode and a lower electrode; a first wiring board electrically connected to the upper electrode, and includes a first, a second, a third plate-shaped portion, the first plate-shaped portion being parallel to the second plate-shaped portion, and the third plate-shaped portion being connected to the first and the second plate-shaped portion; a second wiring board electrically connected to the metal layer, and includes a fifth, a sixth, and a seventh plate-shaped portion, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to the fifth and the sixth plate-shaped portion. The first and the second plate-shaped portion are provided between the fifth and the sixth plate-shaped portion, and the semiconductor chip is positioned between the fifth and the sixth plate-shaped portion.

Claims (22)

1. A semiconductor device comprising:

a substrate;

a metal layer on the substrate;

at least one semiconductor chip provided on the metal layer, the at least one semiconductor chip having an upper electrode and a lower electrode electrically connected to the metal layer;

a first wiring board provided on the substrate, the first wiring board being electrically connected to the upper electrode, the first wiring board including a first plate-shaped portion, a second plate-shaped portion, and a third plate-shaped portion, the first plate-shaped portion, the second plate-shaped portion, and the third plate-shaped portion being perpendicular to the substrate, the first plate-shaped portion being parallel to the second plate-shaped portion, the third plate-shaped portion being perpendicular to the first plate-shaped portion and the second plate-shaped portion, and the third plate-shaped portion being connected to one end of the first plate-shaped portion and one end of the second plate-shaped portion; and

a second wiring board provided on the substrate, the second wiring board being electrically connected to the metal layer, the second wiring board including a fifth plate-shaped portion, a sixth plate-shaped portion, and a seventh plate-shaped portion, the fifth plate-shaped portion, the sixth plate-shaped portion, and the seventh plate-shaped portion being perpendicular to the substrate, the fifth plate-shaped portion being parallel to the sixth plate-shaped portion, the seventh plate-shaped portion being perpendicular to the fifth plate-shaped portion and the sixth plate-shaped portion, and the seventh plate-shaped portion being connected to one end of the fifth plate-shaped portion and one end of the sixth plate-shaped portion,

wherein the first plate-shaped portion and the second plate-shaped portion are provided between the fifth plate-shaped portion and the sixth plate-shaped portion, and

the at least one semiconductor chip is positioned between a plane including the fifth plate-shaped portion and a plane including the sixth plate-shaped portion.

2. The semiconductor device according to claim 1 , wherein

the first wiring board has a fourth plate-shaped portion, the fourth plate-shaped portion is parallel to the third plate-shaped portion, the fourth plate-shaped portion is connected to the other end of the first plate-shaped portion and the other end of the second plate-shaped portion,

the second wiring board has an eighth plate-shaped portion, the eighth plate-shaped portion is parallel to the seventh plate-shaped portion, and the eighth plate-shaped portion is connected to the other end of the fifth plate-shaped portion and the other end of the sixth plate-shaped portion.

3. The semiconductor device according to claim 1 , wherein

the at least one semiconductor chip is a plurality of semiconductor chips,

the first wiring board has a plurality of connecting portions, and

each of the upper electrode of the plurality of semiconductor chips and each of the connection portions are connected to each other.

4. The semiconductor device according to claim 1 , wherein the first wiring board and the upper electrode are electrically connected to each other with a bonding wire interposed between the first wiring board and the upper electrode.

5. The semiconductor device according to claim 1 , wherein a slit is provided in at least one of the first wiring board and the second wiring board.

6. The semiconductor device according to claim 1 , wherein a dielectric layer is provided between the first plate-shaped portion and the fifth plate-shaped portion and between the second plate-shaped portion and the sixth plate-shaped portion.

7. The semiconductor device according to claim 1 , wherein a distance between the first plate-shaped portion and the fifth plate-shaped portion and a distance between the second plate-shaped portion and the sixth plate-shaped portion are 2 mm or smaller.

8. The semiconductor device according to claim 1 , further comprising a resin case, wherein the substrate, the at least one semiconductor chip, the first wiring board, and the second wiring board are provided in the resin case.

9. The semiconductor device according to claim 1 , wherein the at least one semiconductor chip is positioned between a plane including the first plate-shaped portion and a plane including the second plate-shaped portion.

10. The semiconductor device according to claim 2 , wherein the at least one semiconductor chip is positioned between a plane including the seventh plate-shaped portion and a plane including the eighth plate-shaped portion.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 7, 2019
From: MATSUYAMA, HIROSHI
To: KABUSHIKI KAISHA TOSHIBA; TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
Reel/Frame 048265/0378 →
Priority Claims (1)
JP 2018-173126 · Sep 14, 2018 · national
Continuity (1)
Related Publication 20200091118A1 · Mar 19, 2020
Cited By (1)
US 12,355,015