IP Library Granted Patent US 10,453,408
Granted Patent B2
US 10,453,408 · App. 16/270,036 · Granted Oct 22, 2019

Surface display device with a non-rectangular display surface shape and electronic device including same

Inventors: Hiroshi Haga (Kanagawa, JP); Hideki Asada (Kanagawa, JP); Setsuo Kaneko (Kanagawa, JP)
Assignee: TIANMA JAPAN, LTD.
G09G3/3648G02F1/134336G02F1/136286G09G3/18G09G2300/043G09G2300/0426G09G2310/0232G09G2310/0267G09G2320/0214
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Quick Facts
Patent No.
US 10,453,408
App. No.
16/270,036
Granted
Oct 22, 2019
Kind
B2
Abstract

Disclosed is a display device for use of a surface display of an arbitrary shape, including a plural number of display element units, each made up of a circuit that forms a single stage of a scanning circuit and a pixel circuit connected to an output of the scanning circuit, are arranged in a unicursal fashion on a display substrate.

Claims (26)

1. A display device comprising:

a plurality of stages of unit circuits arranged in a cascade connection to form a scanning circuit,

each of the unit circuits including an input node to receive a scanning signal, a clock input node to receive a clock signal and an output node to output the scanning signal,

each of the unit circuits, responsive to the clock signal received at the clock input node, outputting, from the output node thereof, the scanning signal received at a scanning signal input terminal or received at the input node thereof from a preceding unit circuit to transfer the scanning signal to a succeeding unit circuit from the output node thereof and supplying the scanning signal from the output node thereof to a pixel circuit arranged in a stage corresponding to each of the unit circuits;

a plurality of the pixel circuits, each of the pixel circuits including:

a display element having a first end connected to a common electrode; and

a switch transistor adapted to be turned on and off by the scanning signal supplied thereto from the output node of a corresponding stage of the unit circuit, the switch transistor arranged between a terminal to which a data signal is supplied and a second end of the display element; and

a wiring that is connected in common to terminals to which a plurality of the data signals are applied, wherein a voltage signal corresponding to a grayscale level to be displayed by the display element is sequentially applied to the wiring with a clock cycle,

wherein a plurality of the display elements are arranged in a two-dimensional directions to form a display area, with the scanning circuit disposed inside the display area, as viewed in a planer view,

wherein the scanning circuit and the pixel circuits are formed on a non-rectangular substrate with one or more edges being curved, as viewed in a planer view, and

the display area, inside of which the scanning circuit is formed, is formed along the edge of the substrate,

wherein with respect to a linear array of an array of the display elements, a part of the scanning circuit is disposed between two adjacent linear arrays of the display elements.

2. A display device comprising:

a plurality of stages of unit circuits arranged in a cascade connection to form a scanning circuit,

each of the unit circuits including an input node to receive a scanning signal, a clock input node to receive a clock signal and an output node to output the scanning signal,

each of the unit circuits, responsive to the clock signal received at the clock input node, outputting, from the output node thereof, the scanning signal received at a scanning signal input terminal or received at the input node thereof from a preceding unit circuit to transfer the scanning signal to a succeeding unit circuit from the output node thereof and supplying the scanning signal from the output node thereof to a pixel circuit arranged in a stage corresponding to each of the unit circuits;

a plurality of the pixel circuits, each of the pixel circuits including:

a display element having a first end connected to a common electrode; and

a switch transistor adapted to be turned on and off by the scanning signal supplied thereto from the output node of a corresponding stage of the unit circuit, the switch transistor arranged between a terminal to which a data signal is supplied and a second end of the display element; and

a wiring that is connected in common to terminals to which a plurality of the data signals are applied, wherein a voltage signal corresponding to a grayscale level to be displayed by the display element is sequentially applied to the wiring with a clock cycle,

wherein a plurality of the display elements are arranged in a two-dimensional directions to form a display area, with the scanning circuit disposed inside the display area, as viewed in a planer view,

wherein the scanning circuit and the pixel circuits are formed on a non-rectangular substrate with one or more edges being curved, as viewed in a planer view, and

the display area, inside of which the scanning circuit is formed, is formed along the edge of the substrate,

wherein a part of said scanning circuit is arranged between neighboring ones of the pixel circuits or underneath the pixel circuit.

3. An electronic device including the display device as set forth in claim 1 .

4. An electronic device including the display device as set forth in claim 2 .

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 30, 2019
From: TIANMA JAPAN, LTD. (FORMERLY NLT TECHNOLOGIES, LTD.)
To: TIANMA MICROELECTRONICS CO., LTD.
Reel/Frame 050582/0869 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 8, 2019
From: HAGA, HIROSHI; ASADA, HIDEKI; KANEKO, SETSUO
To: NEC LCD TECHNOLOGIES, LTD.
Reel/Frame 048272/0378 →
CHANGE OF NAME Recorded Feb 8, 2019
From: NLT TECHNOLOGIES, LTD.
To: TIANMA JAPAN, LTD.
Reel/Frame 048272/0414 →
CHANGE OF NAME Recorded Feb 8, 2019
From: NEC LCD TECHNOLOGIES, LTD.
To: NLT TECHNOLOGIES, LTD.
Reel/Frame 048290/0036 →
Priority Claims (1)
JP 2006-280234 · Oct 13, 2006 · national
Continuity (5)
Division 15982081 · May 17, 2018
Division 14794845 · Jul 9, 2015
Division 14288950 · May 28, 2014
Division 11871173 · Oct 12, 2007
Related Publication 20190189073A1 · Jun 20, 2019