Interconnect with high quality ultra-low-k dielectric
Semiconductor devices and methods for forming the semiconductor devices include first line trenches formed in a dielectric layer on a substrate. Sacrificial spacers are formed on sidewalls of the dielectric layer in the first line trenches. Second line trenches are formed in the dielectric layer, the first line trenches and the second line trenches including alternating rows of trenches separated by the sacrificial spacers. The first line trenches and the second line trenches are filled with conductive material to form conductive lines. The sacrificial spacers are replaced with an isolation material.
1. A method for forming a semiconductor device, the method comprising:
forming first line trenches in a dielectric layer on a substrate;
forming sacrificial spacers on sidewalls of the dielectric layer in the first line trenches;
forming second line trenches in the dielectric layer, the first line trenches and the second line trenches including alternating rows of trenches separated by the sacrificial spacers;
filling the first line trenches and the second line trenches with conductive material to form conductive lines; and
replacing the sacrificial spacers with an isolation material.
2. The method as recited in claim 1 , further including patterning a first etch mask over the dielectric layer for the first line trenches.
3. The method as recited in claim 1 , further including patterning a second etch mask over the dielectric layer and the first line trenches for the second line trenches.
4. The method as recited in claim 1 , wherein replacing the sacrificial spacers includes:
removing the sacrificial spacers to open isolation regions between the first conductive lines and the second conductive lines; and
filling the isolation regions with the isolation material.
5. The method as recited in claim 4 , wherein the isolation includes an ultra-low-k dielectric.
6. The method as recited in claim 4 , wherein depositing the isolation material includes forming an air gap within the isolation material in each of the isolation regions.
7. The method as recited in claim 1 , wherein one or more of the rows of trenches include a plurality of trench segments separated by material of the dielectric layer.
8. The method as recited in claim 1 , wherein the sacrificial spacers are replaced with the isolation material including a material different from a material of the dielectric layer.
9. The method as recited in claim 1 , wherein forming the first line trenches includes performing anisotropic etching through an etch mask selective to the dielectric layer and the substrate.
10. A method for forming a semiconductor device, the method comprising:
patterning a first etch mask over a dielectric layer on a substrate corresponding to a first pattern;
etching first line trenches into the dielectric layer through the first etch mask;
removing the first etch mask;
forming sacrificial spacers on sidewalls of the dielectric layer in the first line trenches;
patterning a second etch mask over the dielectric layer and the first line trenches corresponding to second pattern, the first pattern and the second pattern corresponding to alternating rows of first conductive lines and second conductive lines;
etching second line trenches into the dielectric layer through the second etch mask;
filling the first line trenches and the second line trenches with a conductive material to form the first conductive lines and the second conductive lines; and
replacing the sacrificial spacers with an isolation material.
11. The method as recited in claim 10 , wherein replacing the sacrificial spacers includes:
removing the sacrificial spacers to open isolation regions between the first conductive lines and the second conductive lines; and
filling the isolation regions with the isolation material.
12. The method as recited in claim 11 , wherein the isolation includes an ultra-low-k dielectric.
13. The method as recited in claim 11 , wherein depositing the isolation material includes forming an air gap within the isolation material in each of the isolation regions.
14. The method as recited in claim 10 , wherein one or more of the alternating rows of conductive lines include a plurality of conductive line segments separated by material of the dielectric layer sandwiched between the isolation regions corresponding to each of the plurality of conductive line segments.
15. The method as recited in claim 10 , wherein the sacrificial spacers are replaced with the isolation material including a material different from a material of the dielectric layer.
16. The method as recited in claim 10 , wherein etching the first line trenches includes performing anisotropic etching through the first line mask selective to the dielectric layer and the substrate.