Semiconductor memory and method of manufacturing the semiconductor memory

1. A semiconductor memory comprising:

first and second areas arranged in a first direction;

an active region including part of each of the first and second areas;

a non-active region including part of each of the first and second areas;

a first stacked body in the active region, the first stacked body including first insulators and first conductors which are alternately stacked, each of the first conductors including a terraced portion that does not overlap the upper first conductor in the second area;

a plurality of first pillars each penetrating the first stacked body in the first area; an intersection between the first pillar and the first conductor functions as a memory cell;

a first contact on a terraced portion of a first conductor in a first interconnect layer;

a second stacked body in the non-active region, the second stacked body including second insulators and second conductors which are alternately stacked, each of the second conductors including a terraced portion that does not overlap the upper second conductor in the second area; and

a second contact that is in contact with a terraced portion of a second conductor in the first interconnect layer and a terraced portion of a second conductor in a second interconnect layer different from the first interconnect layer.

2. The memory of claim 1 , wherein:

the first contact and the second contact are each provided like a pillar; and

an outside diameter of the second contact is larger than an outside diameter of the first contact in a section parallel to a surface of a substrate.

3. The memory of claim 1 , further comprising a third conductor above the first conductors,

wherein:

the third conductor is electrically connected to the first contact; and

no interconnect above the second contact is electrically connected to the second contact.

4. The memory of claim 1 , wherein:

in the second area, the second conductor in the first interconnect layer has a first terraced portion that does not overlap the upper second conductor, the second conductor in the second interconnect layer has a second terraced portion that does not overlap the upper second conductor, a second conductor in a third interconnect layer different from the first and second interconnect layers has a third terraced portion that does not overlap the upper second conductor, and a second conductor in a fourth interconnect layer different from the first to third interconnect layers has a fourth terraced portion that does not overlap the upper second conductor:

the first terraced portion and the second terraced portion are adjacent to each other in one of the first direction and a second direction that intersects the first direction;

the third terraced portion and the fourth terraced portion are adjacent to each other in one of the first direction and the second direction;

the first terraced portion and the third terraced portion are adjacent to each other in one of the second direction and the first direction;

the second terraced portion and the fourth terraced portion are adjacent to each other in one of the second direction and the first direction; and

the second contact is in contact with each of the first to fourth terraced portions.

5. The memory of claim 1 , wherein:

in the second area, the second conductor in the first interconnect layer has a first terraced portion that does not overlap the upper second conductor, the second conductor in the second interconnect layer has a second terraced portion that does not overlap the upper second conductor, and a second conductor in a third interconnect layer different from the first and second interconnect layers has a third terraced portion that does not overlap the upper second conductor;

the first to third terraced portions are arranged in one of the first direction and a second direction that intersects the first direction; and

the second contact is in contact with each of the first to third terraced portions.

6. The memory of claim 1 , wherein a position of an upper end of the first contact and a position of an upper end of the second contact are substantially equal to each other in a stack direction of the first stacked body.

7. The memory of claim 1 , wherein the first contact and the second contact include a same material.

8. The memory of claim 1 , further comprising a plurality of second pillars each penetrating the second stacked body in the first area.

9. The memory of claim 8 , further comprising a fourth conductor used as a bit line,

wherein at least one of the first pillars is electrically connected to the fourth conductor, and none of the second pillars is electrically connected to the fourth conductor.

10. A semiconductor memory comprising:

first and second areas arranged in a first direction;

an active region including part of each of the first and second areas;

a non-active region including part of each of the first and second areas;

a first stacked body in the active region, the first stacked body including first insulators and first conductors which are alternately stacked, each of the first conductors including a terraced portion that does not overlap the upper first conductor in the second area;

a plurality of first pillars each penetrating the first stacked body in the first area, an intersection between the first pillar and the first conductor functions as a memory cell;

a first contact on a terraced portion of a first conductor in a first interconnect layer;

a second stacked body in the non-active region, the second stacked body including second insulators and second conductors which are alternately stacked, each of the second conductors including a terraced portion that does not overlap the upper second conductor in the second area; and

a second contact that is in contact with at least one of the terraced portions of the second conductors in the second area,

wherein:

the first contact and the second contact are each provided like a pillar; and

an outside diameter of the second contact is larger than an outside diameter of the first contact in a section parallel to a surface of a substrate.

11. The memory of claim 10 , further comprising a third conductor above the first conductors,

wherein:

the third conductor is electrically connected to the first contact; and

no interconnect above the second contact is electrically connected to the second contact.

12. The memory of claim 10 , wherein:

in the second area, a second conductor in the first interconnect layer has a first terraced portion that does not overlap the upper second conductor, a second conductor in a second interconnect layer different from the first interconnect layer has a second terraced portion that does not overlap the upper second conductor, a second conductor in a third interconnect layer different from the first and second interconnect layers has a third terraced portion that does not overlap the upper second conductor, and a second conductor in a fourth interconnect layer different from the first to third interconnect layers has a fourth terraced portion that does not overlap the upper second conductor;

the first terraced portion and the second terraced portion are adjacent to each other in one of the first direction and a second direction that intersects the first direction;

the third terraced portion and the fourth terraced portion are adjacent to each other in one of the first direction and the second direction;

the first terraced portion and the third terraced portion are adjacent to each other in one of the second direction and the first direction;

the second terraced portion and the fourth terraced portion are adjacent to each other in one of the second direction and the first direction; and

the second contact is in contact with each of the first to fourth terraced portions.

13. The memory of claim 10 , wherein:

in the second area, a second conductor in the first interconnect layer has a first terraced portion that does not overlap the upper second conductor, a second conductor in a second interconnect layer different from the first interconnect layer has a second terraced portion that does not overlap the upper second conductor, and a second conductor in a third interconnect layer different from the first and second interconnect layers has a third terraced portion that does not overlap the upper second conductor;

the first to third terraced portions are arranged in one of the first direction and a second direction that intersects the first direction; and

the second contact is in contact with each of the first to third terraced portions.

14. The memory of claim 10 , wherein a position of an upper end of the first contact and a position of an upper end of the second contact are substantially equal to each other in a stack direction of the first stacked body.

15. The memory of claim 10 , wherein the first contact and the second contact include a same material.

16. The memory of claim 10 , further comprising a plurality of second pillars each penetrating the second stacked body in the first area.

17. The memory of claim 16 , further comprising a fourth conductor used as a bit line,

wherein at least one of the first pillars is electrically connected to the fourth conductor, and none of the second pillars is electrically connected to the fourth conductor.