Method for fabricating semiconductor device

1. A method for fabricating a semiconductor device, the method comprising:

forming a first wiring layer, the first wiring layer including a first metal wiring and a first interlayer insulating film wrapping the first metal wiring on a substrate;

forming a first via layer, the first via layer including a first via that is in electrical connection with the first metal wiring, and a second interlayer insulating film wrapping the first via on the first wiring layer; and

forming a second wiring layer, the second wiring layer including a second metal wiring that is in electrical connection with the first via, and a third interlayer insulating film wrapping the second metal wiring on the first via layer, wherein:

the third interlayer insulating film contains deuterium and is formed through chemical vapor deposition using a first gas and a second gas that contains hydrogen,

the first gas includes one or more of SiD 4 , D 2 O, ND 3 , Si 2 D 6 , or (C 2 H 5 ) 3 SiD, and

forming the second wiring layer includes:

forming the second metal wiring on the first via layer, forming the second metal wiring including forming a second metal wiring material on the second interlayer insulating film and then patterning the second metal wiring material; and

after patterning the second metal wiring material, forming the third interlayer insulating film so as to wrap the second metal wiring.

2. The method as claimed in claim 1 , further comprising:

after forming the second wiring layer,

forming a second via layer, the second via layer including a second via that is in electrical connection with the second metal wiring, and a fourth interlayer insulating film wrapping the second via on the second wiring layer; and

forming a third wiring layer, the third wiring layer including a third metal wiring that is in electrical connection with the second via, and a fifth interlayer insulating film wrapping the third metal wiring on the second via layer.

3. The method as claimed in claim 2 , wherein forming the third wiring layer includes:

forming the fifth interlayer insulating film on the second via layer;

forming a second trench by etching the fifth interlayer insulating film; and

forming the third metal wiring filling the second trench.

4. The method as claimed in claim 1 , further comprising:

after forming the second wiring layer,

forming a sixth interlayer insulating film on the second wiring layer;

forming a third trench and forming a fourth trench on the third trench by etching the sixth interlayer insulating film; and

forming a third via filling the third trench and being in electrical connection with the second metal wiring, and forming a fourth metal wiring filling the fourth trench and being in electrical connection with the third via.

5. The method as claimed in claim 1 , further comprising forming an air-gap in the third interlayer insulating film.

6. The method as claimed in claim 1 , wherein the third interlayer insulating film is formed through plasma enhanced chemical vapor deposition at a temperature less than 450° C.

7. The method as claimed in claim 1 , wherein:

a deuterium source is not used in forming the second interlayer insulating film such that the second interlayer insulating film does not contain added deuterium, and

the third interlayer insulating film is in direct contact with the second interlayer insulating film.

8. A method for fabricating a semiconductor device, the method comprising:

forming a first interlayer insulating film including a first trench on a substrate;

forming a first metal wiring filling the first trench;

forming a first etch stop film covering the first interlayer insulating film and the first metal wiring;

forming a second interlayer insulating film including a second trench penetrating through the first etch stop film on the first etch stop film;

forming a first via filling the second trench;

forming a second metal wiring material on the second interlayer insulating film and the first via, and then patterning the second metal wiring material to form a second metal wiring on the first via; and

after patterning the second metal wiring material, forming a third interlayer insulating film so as to cover a side surface and an upper surface of the second metal wiring on the second interlayer insulating film, wherein:

the third interlayer insulating film includes deuterium and is formed through chemical vapor deposition using a first gas and a second gas different from the first gas,

the first gas includes one or more of SiD 4 , D 2 O, ND 3 , Si 2 D 6 , or (C 2 H 5 ) 3 SiD, and

the second gas contains hydrogen.

9. The method as claimed in claim 8 , further comprising:

after forming the third interlayer insulating film,

forming a second etch stop film covering the third interlayer insulating film;

forming a fourth interlayer insulating film including a third trench penetrating through a portion of the third interlayer insulating film and the second etch stop film on the second etch stop film;

forming a second via filling the third trench;

forming a fifth interlayer insulating film including a fourth trench on the fourth interlayer insulating film; and

forming a third metal wiring filling the fourth trench.

10. The method as claimed in claim 8 , wherein:

the first to third interlayer insulating films include silicon oxide,

the first etch stop film includes silicon nitride, and

a deuterium source is not used in forming the first and second interlayer insulating films such that the first and second interlayer insulating films do not contain added deuterium.

11. The method as claimed in claim 8 , wherein forming the third interlayer insulating film further includes:

using a carrier gas containing one or more of Ar, O 2 , N 2 , H 2 , D 2 , D 2 O, w ND 3 , NDHe, O 3 , NH 3 , Kr, or Xe.

12. The method as claimed in claim 8 , further comprising forming an air-gap in the third interlayer insulating film.