Switched capacitor vector-matrix multiplier
Methods and apparatuses enable a general-purpose low power analog vector-matrix multiplier. A switched capacitor matrix multiplier may comprise a plurality of successive approximate registers (SAR) operating in parallel, each SAR having a SAR digital output; and a plurality of Analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each MAC unit is connected in series to a SAR of the plurality of SARs.
1. A switched capacitor matrix multiplier, comprising:
a plurality of successive approximation registers (SAR) operating in parallel, each SAR of the plurality of SARs having a SAR digital output; and
a plurality of analog Multiply-and-Accumulate (MAC) units for multiplying and accumulating and scaling bit-wise products of a digital weight matrix with a digital input vector, wherein each analog MAC unit of the plurality of analog MAC units is connected in series to a SAR of the plurality of SARs.
2. The switched capacitor matrix multiplier of claim 1 , wherein a successive approximation register comprises:
a comparator; and
a state machine.
3. The switched capacitor matrix multiplier of claim 2 , wherein each analog MAC unit of the plurality of analog MAC units comprises
one or more of a SAR capacitor, an AND gate, an inverter, or a multiplexer.
4. The switched capacitor matrix multiplier of claim 3 , wherein the SAR further comprises a SAR local memory.
5. The switched capacitor matrix multiplier of claim 4 , wherein the SAR local memory is configured to store bit-wise weight and input values.
6. The switched capacitor matrix multiplier of claim 2 , wherein the comparator compares a reference voltage V ref to an output voltage of the plurality of analog MAC units.
7. The switched capacitor matrix multiplier of claim 2 , wherein an output of the comparator is an input to the state machine.
8. The switched capacitor matrix multiplier of claim 2 , wherein the SAR further comprises seven reset switches.
9. The switched capacitor matrix multiplier of claim 1 , wherein bit-wise multiplication of a digital weight matrix with a digital input vector is performed by the plurality of SARs using only SAR capacitors.