Vertical FET with reduced parasitic capacitance
A method for reducing parasitic capacitance of a semiconductor structure is provided. The method includes forming a fin structure over a substrate, forming a first source/drain region between the fin structure and the substrate, forming first spacers adjacent the fin structure, forming second spacers adjacent the first source/drain region and recessing the first source/drain region in exposed areas. The method further includes forming a shallow trench isolation (STI) region within the exposed areas of the recessed first source/drain region, depositing a bottom spacer over the STI region, forming a metal gate stack over the bottom spacer, depositing a top spacer over the metal gate stack, cutting the metal gate stack, forming a second source/drain region over the fin structure, and forming contacts such the STI region extends a length between the metal gate stack and the first source/drain region.
1. A method for reducing parasitic capacitance of a semiconductor structure, the method comprising:
forming first spacers adjacent a fin structure and second spacers adjacent a first source/drain region;
forming a shallow trench isolation (STI) region in direct contact with a portion of the first spacers and a portion of the second spacers; and
depositing a bottom spacer in direct contact with the STI region such that the first spacers are selectively removed before the bottom spacer is deposited over the STI region.
2. The method of claim 1 , wherein the first source/drain region is formed under the fin structure.
3. The method of claim 2 , wherein the bottom spacer defines a reverse-stepped structural configuration.
4. The method of claim 3 , further comprising forming a metal gate stack over the bottom spacer.
5. The method of claim 4 , wherein the metal gate stack is formed such that gate-to-source/drain capacitances are reduced by extending the STI region between the metal gate stack and the first source/drain region.
6. The method of claim 5 , further comprising depositing a top spacer over the metal gate stack.
7. The method of claim 6 , further comprising cutting the metal gate stack after forming the first spacers.
8. The method of claim 7 , further comprising forming a second source/drain region over the fin structure after cutting the metal gate stack.
9. The method of claim 8 , further comprising forming contacts such that the STI region extends a length between the metal gate stack and the first source/drain region.
10. The method of claim 9 , wherein the STI region covers the second spacers adjacent the first source/drain region in their entirety.
11. A semiconductor structure for reducing parasitic capacitance, the structure comprising:
first spacers disposed adjacent a fin structure and second spacers disposed adjacent a first source/drain region;
a shallow trench isolation (STI) region disposed in direct contact with a portion of the first spacers and a portion of the second spacers; and
a bottom spacer disposed in direct contact with the STI region such that the first spacers are selectively removed before the bottom spacer is deposited over the STI region.
12. The structure of claim 11 , wherein the bottom spacer defines a reverse-stepped structural configuration.
13. The structure of claim 12 , wherein a metal gate stack is disposed over the bottom spacer.
14. The structure of claim 13 , wherein the metal gate stack is disposed such that gate-to-source/drain capacitances are reduced by extending the STI region between the metal gate stack and the first source/drain region.
15. The structure of claim 14 , wherein a top spacer is disposed over the metal gate stack.
16. The structure of claim 15 , wherein the metal gate stack is cut after forming the first spacers.
17. The structure of claim 16 , wherein a second source/drain region is disposed over the fin structure after cutting the metal gate stack.
18. The structure of claim 17 , wherein contacts are created such that the STI region extends a length between the metal gate stack and the first source/drain region.
19. The structure of claim 18 , wherein the STI region covers the second spacers adjacent the first source/drain region in their entirety.
20. The structure of claim 19 , wherein a distance between the metal gate stack and the first source/drain region is greater than about 10 nm.