Radar device, radar system and method for generating a sampling clock signal

1. A radar device, comprising:

a data communication input interface configured to:

receive a data clock signal for a data bus;

an analog to digital converter configured to:

sample a signal at time instants given by a synchronized sampling clock signal; and

a sampling clock generation circuit configured to:

perform synchronization of a sampling clock signal to a predetermined cycle of the data clock signal, and

generate the synchronized sampling clock signal based on performing the synchronization.

2. The radar device of claim 1 , wherein the sampling clock generation circuit comprises a frequency divider circuit configured to:

reduce a frequency of the data clock signal to generate the synchronized sampling clock signal.

3. The radar device of claim 1 , wherein the sampling clock generation circuit is further configured to:

modify a phase of the sampling clock signal.

4. The radar device of claim 3 , wherein the sampling clock generation circuit, when modifying the phase of the sampling clock signal, is to:

modify the phase based on at least one environmental parameter.

5. The radar device of claim 1 , wherein the sampling clock generation circuit, when performing the synchronization of the sampling clock signal, is configured to:

perform the synchronization of the sampling clock signal based on receiving a ramp start signal.

6. The radar device of claim 1 , wherein the sampling clock generation circuit is further configured to:

determine the predetermined cycle of the data clock signal by selecting the predetermined cycle of the data clock signal based on receiving a ramp start signal.

7. The radar device of claim 1 , wherein the analog to digital converter, when sampling the signal at the time instants given by the synchronized sampling clock signal, is configured to:

sample a downconverted radar signal of a receiver of the radar device.

8. The radar device of claim 7 , further comprising one or more of:

a mixer circuit configured to down-mix a radar signal with a local oscillator signal to generate the downconverted radar signal,

a receive antenna coupled to the mixer circuit and configured to receive the radar signal, or

a low noise amplifier coupled between the receive antenna and the mixer circuit.

9. The radar device of claim 1 , wherein the data communication input interface is further configured to:

receive payload data via the data bus.

10. The radar device of claim 1 , wherein the data communication input interface is configured to:

receive the data clock signal via the data bus.

11. The radar device of claim 1 , wherein the sampling clock generation circuit is further configured to:

generate a frequency of the synchronized sampling clock signal using a phase locked loop (PLL).

12. A radar device, comprising:

an oscillator interface configured to:

receive an oscillator signal generated by an external oscillator;

a data clock generation circuit configured to:

generate a data clock signal for a data bus based on the oscillator signal;

a data communication output interface configured to:

output the data clock signal; and

a sampling clock generation circuit configured to:

perform synchronization of a sampling clock signal to a predetermined cycle of the data clock signal, and

generate a synchronized sampling clock signal based on performing the synchronization.

13. The radar device of claim 12 , wherein the data communication output interface is further configured to:

output payload data.

14. The radar device of claim 12 , further comprising:

an analog to digital converter configured to:

sample a signal at time instants given by the synchronized sampling clock signal.

15. The radar device of claim 12 , further comprising:

an input interface configured to receive another data clock signal; and

wherein the sampling clock generation circuit is further configured to:

perform synchronization of another sampling clock based on the other data clock signal.

16. A radar system comprising:

a first radar device, comprising:

an oscillator interface configured to:

receive an oscillator signal;

a data clock generation circuit configured to:

generate a data clock signal for a data bus based on the oscillator signal; and

a data communication output interface configured to:

output the data clock signal;

a second radar device, comprising:

a data communication input interface configured to:

receive the data clock signal;

an analog to digital converter configured to:

sample a signal according to a synchronized sampling clock signal; and

a sampling clock generation circuit configured to:

perform synchronization of a sampling clock signal to a predetermined cycle of the data clock signal, and

generate the synchronized sampling clock signal based on performing the synchronization; and

the data bus connecting the data communication output interface and the data communication input interface.

17. The radar system of claim 16 , further comprising:

an oscillator circuit coupled to the oscillator interface of the first radar device, the oscillator circuit being configured to generate the oscillator signal.

18. The radar system of claim 16 , further comprising:

a common printed circuit board on which the first radar device and the second radar device are mounted.

19. The radar system of claim 16 , further comprising:

a third radar device, comprising:

a data communication input interface configured to:

receive the data clock signal from the second radar device;

an analog to digital converter configured to:

sample another signal according to another synchronized sampling clock signal; and

a sampling clock generation circuit configured to:

generate the other synchronized sampling clock signal based on the data clock signal.

20. The radar system of claim 16 , further comprising:

a third radar device, comprising:

a data communication input interface configured to:

receive the data clock signal from the first radar device;

an analog to digital converter configured to:

sample another signal according to another synchronized sampling clock signal; and

a sampling clock generation circuit configured to:

generate the other synchronized sampling clock signal based on the data clock signal.