IP Library › Granted Patent US 11,038,029
Granted Patent B2
US 11,038,029 · App. 16/277,262 · Granted Jun 15, 2021

Semiconductor device structure and method for forming the same

Inventors: Hsueh-Wen Tsau (Miaoli County, TW); Chun-I Wu (Taipei, TW); Ziwei Fang (Hsinchu, TW); Huang-Lin Chao (Hillsboro, OR); I-Ming Chang (ShinChu, TW); Chung-Liang Cheng (Changhua County, TW); Chih-Cheng Lin (Taipei, TW)
Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
H01L29/401H01L21/28247H01L21/76831H01L21/76843H01L23/53223H01L23/53252H01L23/53266H01L29/42392H01L29/4966H01L29/66795H01L29/785H01L21/28088H01L21/28568H01L23/5226H01L29/0673
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Quick Facts
Patent No.
US 11,038,029
App. No.
16/277,262
Granted
Jun 15, 2021
Kind
B2
Abstract

A method for forming a semiconductor device structure is provided. The method includes providing a substrate and an insulating layer over the substrate. The insulating layer has a trench partially exposing the substrate. The method includes forming a gate dielectric layer in the trench. The method includes forming a first metal-containing layer over the gate dielectric layer. The method includes forming a silicon-containing layer over the first metal-containing layer. The method includes forming a second metal-containing layer over the silicon-containing layer. The method includes forming a gate electrode layer in the trench and over the second metal-containing layer.

Claims (42)

1. A method for forming a semiconductor device structure, comprising:

providing a substrate and an insulating layer over the substrate, wherein the insulating layer has a trench partially exposing the substrate;

forming a gate dielectric layer in the trench;

forming a first metal-containing layer over the gate dielectric layer;

forming a silicon-containing layer over the first metal-containing layer, wherein the silicon-containing layer is thinner than the first metal-containing layer;

forming a second metal-containing layer over the silicon-containing layer; and

forming a gate electrode layer in the trench and over the second metal-containing layer.

2. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the silicon-containing layer is made of silicon oxide.

3. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the forming of the silicon-containing layer over the first metal-containing layer comprises:

forming a silicon layer over the first metal-containing layer; and

oxidizing the silicon layer.

4. The method for forming the semiconductor device structure as claimed in claim 3 , wherein the forming of the silicon layer over the first metal-containing layer comprises:

applying a silicon-containing compound on the first metal-containing layer, wherein the applying of the silicon-containing compound on the first metal-containing layer and the forming of the first metal-containing layer over the gate dielectric layer are performed in a same chamber.

5. The method for forming the semiconductor device structure as claimed in claim 4 , wherein the silicon-containing compound is represented by formula SinH2n+2, and n is an integer from 1 to 10.

6. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the forming of the second metal-containing layer over the silicon-containing layer comprises:

performing an atomic layer deposition process over the silicon-containing layer.

7. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the silicon-containing layer conformally covers the first metal-containing layer.

8. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the silicon-containing layer is thinner than the second metal-containing layer.

9. The method for forming the semiconductor device structure as claimed in claim 1 , wherein the second metal-containing layer is made of titanium nitride.

10. A method for forming a semiconductor device structure, comprising:

providing a substrate, a gate stack, a source/drain structure and an insulating layer, wherein the gate stack is over the substrate, the source/drain structure is in the substrate and adjacent to the gate stack, and the insulating layer is over the substrate and the source/drain structure;

forming a through hole in the insulating layer and exposing the source/drain structure, wherein the through hole has a first inner wall and a second inner wall opposite to the first inner wall;

forming a silicon-containing layer in the through hole to cover the source/drain structure and the first inner wall and the second inner wall of the through hole, wherein the silicon-containing layer continuously extends from the first inner wall to the second inner wall, and the silicon-containing layer has a substantially U shape in a cross-sectional view of the silicon-containing layer;

forming a barrier layer in the through hole and over the silicon-containing layer; and

forming a metal-containing layer in the through hole and over the barrier layer.

11. The method for forming the semiconductor device structure as claimed in claim 10 , wherein the forming of the barrier layer in the through hole and over the silicon-containing layer comprises:

performing an atomic layer deposition process over the silicon-containing layer.

12. The method for forming the semiconductor device structure as claimed in claim 10 , wherein the silicon-containing layer continuously and conformally covers the first inner wall of the through hole, the source/drain structure, and the second inner wall of the through hole.

13. The method for forming the semiconductor device structure as claimed in claim 10 , wherein the silicon-containing layer is made of silicon oxide.

14. The method for forming the semiconductor device structure as claimed in claim 10 , wherein the silicon-containing layer surrounds the metal-containing layer and the barrier layer.

15. A semiconductor device structure, comprising:

a substrate; and

a gate stack over the substrate, wherein the gate stack comprises a gate dielectric layer, a first metal-containing layer, a first silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the first silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the first silicon-containing layer is thinner than the first metal-containing layer.

16. The semiconductor device structure as claimed in claim 15 , further comprising:

an insulating layer over the substrate and surrounding the gate stack.

17. The semiconductor device structure as claimed in claim 16 , further comprising:

a source/drain structure in the substrate and adjacent to the gate stack, wherein the insulating layer covers the source/drain structure; and

a contact structure passing through the insulating layer and connected to the source/drain structure, wherein the contact structure comprises a second silicon-containing layer, a barrier layer, and a third metal-containing layer, the barrier layer is between the second silicon-containing layer and the third metal-containing layer, and the second silicon-containing layer is between the barrier layer and the insulating layer and between the barrier layer and the source/drain structure.

18. The semiconductor device structure as claimed in claim 17 , wherein the barrier layer conformally covers the second silicon-containing layer.

19. The semiconductor device structure as claimed in claim 15 , further comprising:

a semiconductor wire passing through the gate stack, wherein the first silicon-containing layer surrounds the semiconductor wire.

20. The semiconductor device structure as claimed in claim 15 , wherein the first silicon-containing layer is thinner than the second metal-containing layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2019
From: TSAU, HSUEH-WEN; WU, CHUN-I; FANG, ZIWEI; CHAO, HUANG-LIN; CHANG, I-MING; CHENG, CHUNG-LIANG; LIN, CHIH-CHENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 048399/0334 →
Continuity (2)
Provisional Application 62757291 · Nov 8, 2018
Related Publication 20200152746A1 · May 14, 2020