Multi-transistor device including first and second LDMOS transistors having respective drift regions separated in a thickness direction by a shared RESURF layer

1. A multi-transistor device, comprising first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer, a first drain n+ region, and a second drain n+ region, wherein;

the first LDMOS transistor includes a first drift region,

the second LDMOS transistor includes a second drift region,

the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction, and

wherein the first and second drift regions are between the first drain n+ region and the second drain n+ region.

2. The multi-transistor device of claim 1 , further comprising third and fourth LDMOS transistors sharing a second p-type RESURF layer and the second drain n+ region.

3. A multi-transistor device, comprising first and second lateral double-diffused metal-oxide-semiconductor field effect (LDMOS) transistors sharing a first p-type reduced surface field (RESURF) layer and a first drain n+ region, wherein

the first LDMOS transistor includes a first drift region,

the second LDMOS transistor includes a second drift region, and

the first and second drift regions are at least partially separated by the first p-type RESURF layer in a thickness direction;

the multi-transistor device further comprising third and fourth LDMOS transistors sharing a second p-type RESURF layer and a second drain n+ region,

wherein a source region of the first LMDOS transistor is electrically coupled to a source region of the third LDMOS transistor.

4. The multi-transistor device of claim 2 , wherein:

the first LDMOS transistor is separated from the third LDMOS transistor in a lateral direction orthogonal to the thickness direction; and

the second LDMOS transistor is separated from the fourth LDMOS transistor in the lateral direction.

5. The multi-transistor device of claim 4 , wherein:

the first and second LDMOS transistors share a p-body region;

the first LDMOS transistor includes a first source n+ region disposed in the p-body region;

the second LDMOS transistor includes a second source n+ region disposed in the p-body region; and

the first and second LDMOS transistors share a source p+ region disposed in the p-body region.

6. The multi-transistor device of claim 5 , wherein each of the first p-type RESURF layer, the first drain n+ region, the first drift region, the second drift region, the first source n+ region, the second source n+ region, and the source p+ region are part of a silicon semiconductor structure.

7. The multi-transistor device of claim 6 , wherein the first source n+ region is separated from the second source n+ region by the source p+ region.

8. The multi-transistor device of claim 6 , wherein the first p-type RESURF layer adjoins the p-body region in the thickness direction.

9. The multi-transistor device of claim 6 , further comprising:

a first gate conductive layer and a first gate dielectric layer stacked on the silicon semiconductor structure in the thickness direction over the p-body region; and

a second gate conductive layer and a second gate dielectric layer stacked on the silicon semiconductor structure in the thickness direction over the p-body region,

wherein:

the first gate dielectric layer is separated from the second gate dielectric layer in a lateral direction, and

wherein the first gate conductive layer is separated from the second gate conductive layer in the lateral direction.

10. The multi-transistor device of claim 9 , further comprising a shallow trench isolation (STI) region disposed in a trench in the silicon semiconductor structure, the STI region being disposed between the p-body region and the first drain n+ region in the lateral direction.

11. The multi-transistor device of claim 10 , wherein the first gate conductive layer extends at least partially over the STI region in the thickness direction.

12. The multi-transistor device of claim 10 , further comprising:

an inner-layer dielectric (ILD) disposed over the silicon semiconductor structure in the thickness direction; and

a conductive field plate disposed over the ILD in the thickness direction.

13. The multi-transistor device of claim 12 , wherein the conductive field plate is disposed at least partially over the STI region in the thickness direction.

14. The multi-transistor device of claim 12 , wherein the conductive field plate is electrically coupled to the first source n+ region, the second source n+ region, and the source p+ region.

15. The multi-transistor device of claim 6 , further comprising:

a source electrode disposed over the silicon semiconductor structure and contacting each of the first source n+ region, the second n+ region, and the source p+ region; and

a drain electrode disposed over the silicon semiconductor structure and contacting the first drain n+ region.

16. A multi-transistor device, comprising:

a silicon semiconductor structure, including:

a base layer,

a first n-type drift region disposed over the base layer in a thickness direction,

a p-type reduced surface field (RESURF) layer disposed over the first n-type drift region in the thickness direction,

a second n-type drift region disposed over the p-type RESURF layer in the thickness direction,

a p-body region disposed over the p-type RESURF layer in the thickness direction,

first and second source n+ regions disposed in the p-body region, and

first and second drain n+ regions, wherein the first and second n-type drift regions are between the first and second drain n+ regions;

a first gate conductive layer and a first gate dielectric layer stacked on the silicon semiconductor structure in the thickness direction over the p-body region; and

a second gate conductive layer and a second gate dielectric layer stacked on the silicon semiconductor structure in the thickness direction over the p-body region.

17. The multi-transistor device of claim 16 , wherein:

the silicon semiconductor structure further includes a source p+ region disposed in the p-body region; wherein the source p+ region separates the first and second source n+ regions in a lateral direction, the lateral direction being orthogonal to the thickness direction.

18. The multi-transistor device of claim 17 , wherein the drain n+ region is separated from the p-body region in the lateral direction.

19. The multi-transistor device of claim 17 , further comprising a shallow trench isolation (STI) region disposed in a trench in the silicon semiconductor structure, the STI region being disposed between the p-body region and the drain n+ region in the lateral direction.

20. The multi-transistor device of claim 19 , wherein the first gate conductive layer extends at least partially over the STI region in the thickness direction.