Chip embedded integrated voltage regulator
One or more chip-embedded integrated voltage regulators (“CEIVR's”) are configured to provide power to a circuit or chip such as a CPU or GPU and meet power delivery specifications. The CEIVR's, circuit or chip, and power delivery pathways can be included within the same package. The CEIVR's can be separate from the circuit or chip.
1. A method for delivering electrical power, the method comprising:
receiving electrical power having a first voltage;
modifying the electrical power using a power converter to provide electrical power having a second voltage lower than the first voltage;
delivering the electrical power having the second voltage to a processor package that comprises:
an interposer;
a computer processor mounted onto the interposer; and
a plurality of chip-embedded voltage regulators on the interposer, wherein the plurality of chip-embedded voltage regulators are coupled in parallel and are electrically coupled to the computer processor through the interposer, and wherein each of the plurality of chip-embedded voltage regulators comprises:
chip-embedded circuitry including a plurality of power switches configured to modify electrical power; and
an inductor coupled to the chip-embedded circuitry, wherein a footprint of the inductor at least partially overlaps a footprint of the chip-embedded circuitry;
modifying the electrical power provided to the processor package using the plurality of chip-embedded voltage regulators to provide electrical power having a third voltage lower than the second voltage; and
delivering the electrical power having the third voltage to the computer processor through the interposer.
2. The method of claim 1 , wherein the plurality of chip-embedded voltage regulators have a multiple power stage topology.
3. The method of claim 1 , further comprising:
receiving communications in I 2 C or PMBUS protocol communications, and in response, performing at least one of:
changing a setting of at least one of the plurality of chip-embedded voltage regulators; or
reporting information about at least one of the plurality of chip-embedded voltage regulators.
4. The method of claim 1 , wherein the third voltage is about 0.4 V to about 1 V.
5. The method of claim 4 , wherein the second voltage is about 1 V to about 4 V.
6. The method of claim 1 , wherein the inductor is a thin film inductor.
7. The method of claim 1 , wherein the inductor is embedded with the chip-embedded circuitry.
8. The method of claim 1 , wherein the chip-embedded circuitry comprises:
a pulse width modulator (PWM) controller configured to generate one or more PWM signals; and
a driver configured to generate one or more driver signals based at least in part on the one or more PWM signals, wherein the plurality of power switches are driven by the one or more driver signals.
9. The method of claim 1 , wherein the chip-embedded circuitry is embedded in a substrate of the interposer.
10. The method of claim 1 , wherein the chip-embedded circuitry is embedded in a printed circuit board (PCB) between an upper PCB part and a lower PCB part.
11. The method of claim 10 , wherein the PCB is mounted onto the interposer.
12. A packaged electronic device comprising:
a semiconductor die in a package;
a package substrate coupled to the semiconductor die and coupling the semiconductor die to package outputs; and
a chip-embedded power converter that is separate from the semiconductor die, wherein the power converter includes:
an input port configured to receive an input power;
an output port;
chip-embedded circuitry including a plurality of power switches configured to cause a modified power to be provided at the output port;
an inductor coupled to the plurality of power switches; and
an output capacitor coupled to the plurality of power switches;
wherein the power converter is configured to deliver the modified power within the package to the semiconductor die; and
wherein the semiconductor die, the package substrate, and the power converter are included in the same package.
13. The packaged electronic device of claim 12 , wherein the chip-embedded power converter has at least one of a multiple phase or an AC coupled topology.
14. The packaged electronic device of claim 12 , wherein:
the power converter is a direct-current to direct-current (DC-DC) chip-embedded power converter; and
the plurality of power switches are embedded in a printed circuit board (PCB).
15. The packaged electronic device of claim 12 , wherein the semiconductor die includes a semiconductor processor.
16. The packaged electronic device of claim 12 , wherein the inductor is a thin-film inductor.
17. The packaged electronic device of claim 12 , wherein:
a footprint of the inductor overlaps a footprint of the plurality of power switches; and
the plurality of power switches are coupled through one or more vias extending through at least a portion of a PCB to the inductor.
18. The packaged electronic device of claim 12 , wherein the plurality of power switches comprise gallium nitride (GaN) or enhanced gallium nitride (eGaN) power switches.
19. The packaged electronic device of claim 12 , comprising a plurality of chip-embedded power converters that are coupled to each other and coupled to the package substrate.
20. The packaged electronic device of claim 19 wherein the plurality of chip-embedded power converters are coupled in parallel.
21. The packaged electronic device of claim 19 , further comprising:
one or more communication pathways between the semiconductor die and the plurality of chip-embedded power converters, wherein the semiconductor die is configured to enable or disable individual chip-embedded power converters of the plurality of chip-embedded power converters using the one or more communication pathways.
22. The packaged electronic device of claim 19 , further comprising:
a load balancing circuit configured to adjust current sharing across the plurality of chip-embedded power converters.
23. The packaged electronic device of claim 12 , wherein the semiconductor die comprises a processor, and wherein the package substrate is an interposer associated with the processor.
24. A method for assembling a chip-embedded integrated voltage regulator for a package, the method comprising:
providing a package substrate having an electrical connection arrangement for coupling a first semiconductor die to at least one of package inputs or package outputs;
providing a chip-embedded power converter within the package, wherein the chip-embedded power converter includes at least power switches in a second semiconductor die that is chip-embedded; and
coupling, within the package, an output of the chip-embedded power converter to provide power to the first semiconductor die.
25. The method of claim 24 , wherein the chip-embedded power converter has an isolated topology including at least one of: a flyback topology, a forward converter topology, a two transistor forward topology, push-pull topology, full bridge topology, hybrid typology, and half bridge topology.
26. The method of claim 24 , wherein the second semiconductor die is chip-embedded within a printed circuit board (PCB) that is mounted onto the package substrate.
27. The method of claim 24 , wherein the second semiconductor die is chip-embedded in the package substrate.
28. The method of claim 24 , wherein:
the first semiconductor die is a silicon based semiconductor die; and
the second semiconductor die that includes the power switches is an enhanced gallium nitride (eGaN) semiconductor die.
29. The method of claim 24 , further comprising:
coupling an arrangement of a plurality of chip-embedded power converters within the package to the package substrate, each of the plurality of chip-embedded power converters configured to provide power within the package to the first semiconductor die, the chip-embedded power converter being included in the arrangement.
30. The method of claim 29 , further comprising:
performing load balancing among the plurality of chip-embedded power converters by adjusting a current output by at least one of the plurality of chip-embedded power converters.