CONSTANT SCALAR REGISTER ARCHITECTURE FOR ACCELERATION OF DELAY SENSITIVE ALGORITHM
Embodiments of the invention provides a technical solution by modifying or changing unused scalar register to become constant scalar register. By using unused scalar register, aspects of the invention may decrease latency of scalar processing while decrease reiteration in the scalar processing. Embodiments of the invention further reduce the need for separate data store units, such as cache or other storage units.
1 . A graphics processing subsystem, comprising:
a graphics processing unit (GPU) operable to:
identifying a scalar register file associated with the GPU, said scalar register file having a total number of scalar register allocations;
identifying units needed for scalar processing for a kernel execution;
assigning scalar registers in the scalar register file for the kernel execution;
identifying remaining unused units in the scalar register file from the total number of scalar register allocations;
assigning scalar registers of the remaining unused units in the scalar register file to store constant scalar values for the kernel execution;
initializing the scalar register file before the kernel execution; and
launching the kernel execution.
2 . The graphics processing subsystem of claim 1 further comprising upon completion of the kernel execution, recycling the unused units before a next kernel execution.
3 . The graphics processing subsystem of claim 1 , wherein assigning scalar registers in the scalar register file for the kernel execution comprises assigning scalar registers in the scalar register file for one or more threads of the kernel execution.
4 . A computer-implemented method processed by a graphics processing unit comprising:
identifying a scalar register file associated with the GPU, said scalar register file having a total number of scalar register allocations;
identifying units needed for scalar processing for a kernel execution;
assigning scalar registers in the scalar register file for the kernel execution;
identifying remaining unused units in the scalar register file from the total number of scalar register allocations;
assigning scalar registers of the remaining unused units in the scalar register file to store constant scalar values for the kernel execution;
initializing the scalar register file before the kernel execution; and
launching the kernel execution.
5 . The computer-implemented method of claim 4 further comprising upon completion of the kernel execution, recycling the unused units before a next kernel execution.
6 . The computer-implemented method of claim 4 , wherein assigning scalar registers in the scalar register file for the kernel execution comprises assigning scalar registers in the scalar register file for one or more threads of the kernel execution.
7 . A system for reusing unused scalar registers comprising:
a memory that is configured to store instructions for execution by threads;
a graphics processing unit (GPU) configured to execute scalar and vector instructions, wherein the GPU is configured to:
identifying, via a thread controller, a scalar register file associated with the GPU, said scalar register file having a total number of scalar register allocations;
identifying, via the thread controller, units needed for scalar processing for a kernel execution;
assigning, via the thread controller, scalar registers in the scalar register file for the kernel execution;
identifying, via the thread controller, remaining unused units in the scalar register file from the total number of scalar register allocations;
assigning, via the thread controller, scalar registers of the remaining unused units in the scalar register file to store constant scalar values for the kernel execution;
initializing, via the thread controller, the scalar register file before the kernel execution; and
launching, via the thread controller, the kernel execution.
8 . The system of claim 7 further comprising upon completion of the kernel execution, recycling the unused units before a next kernel execution.
9 . The system of claim 7 , wherein assigning scalar registers in the scalar register file for the kernel execution comprises assigning scalar registers in the scalar register file for one or more threads of the kernel execution.