ENHANCED SCALAR VECTOR DUAL PIPELINE ARCHITECTURE WITH CROSS EXECUTION
Embodiments of the invention may provide a technical solution by identifying a set of scalar and vector instructions. The set of scalar and vector instructions may be set to be executed in a kernel. A scalar instruction of the set of scalar and vector instructions is compared to a predefined set of scalar instructions. Based on the comparison, a secondary scalar pipeline is generated for the scalar instruction for processing. The remaining scalar instructions from the set of scalar and vector instructions is assigned to a first scalar pipeline. Vector instructions of the set of scalar and vector instructions are assigned to a vector pipeline.
1 . A computer-implemented method for generating a secondary scalar pipeline comprising:
identifying a set of scalar and vector instructions, said set of scalar and vector instructions being executed in a kernel;
determining a scalar instruction of the set of scalar and vector instructions with a predefined set of scalar instructions;
in response to the determination being positive, generating a secondary scalar pipeline for the scalar instruction for processing;
assigning the remaining scalar instructions from the set of scalar and vector instructions to a first scalar pipeline;
assigning vector instructions of the set of scalar and vector instructions to a vector pipeline; and
initializing the kernel for execution.
2 . The computer-implemented method of claim 1 , wherein the set of scalar and vector instructions are configured to be executed in parallel.
3 . The computer-implemented method of claim 1 , further comprising prioritizing the assigned scalar instructions in the first scalar pipeline.
4 . The computer-implemented method of claim 3 , further comprising assigning a priority flag for the prioritized scalar instructions.
5 . The computer-implemented method of claim 1 , wherein the first scalar pipeline comprises a majority of scalar registers.
6 . The computer-implemented method of claim 1 , wherein the secondary scalar pipeline comprises a subset of scalar registers.
7 . A graphics processing subsystem for generating a secondary scalar pipeline comprising:
a graphics processing unit (GPU) operable to:
identifying a set of scalar and vector instructions, said set of scalar and vector instructions being executed in a kernel;
determining a scalar instruction of the set of scalar and vector instructions with a predefined set of scalar instructions;
in response to the determination being positive, generating a secondary scalar pipeline for the scalar instruction for processing;
assigning the remaining scalar instructions from the set of scalar and vector instructions to a first scalar pipeline;
assigning vector instructions of the set of scalar and vector instructions to a vector pipeline; and
initializing the kernel for execution.
8 . The graphics processing subsystem of claim 7 , wherein the set of scalar and vector instructions are configured to be executed in parallel.
9 . The graphics processing subsystem of claim 7 , further comprising prioritizing the assigned scalar instructions in the first scalar pipeline.
10 . The graphics processing subsystem of claim 9 , further comprising assigning a priority flag for the prioritized scalar instructions.
11 . The graphics processing subsystem of claim 7 , wherein the first scalar pipeline comprises a majority of scalar registers.
12 . The graphics processing subsystem of claim 7 , wherein the secondary scalar pipeline comprises a subset of scalar registers.
13 . A system for generating a secondary scalar pipeline comprising:
a memory that is configured to store instructions for execution by threads;
a graphics processing unit (GPU) configured to execute scalar and vector instructions, wherein the GPU is configured to:
identifying a set of scalar and vector instructions, said set of scalar and vector instructions being executed in a kernel;
determining a scalar instruction of the set of scalar and vector instructions with a predefined set of scalar instructions;
in response to the determination being positive, generating a secondary scalar pipeline for the scalar instruction for processing;
assigning the remaining scalar instructions from the set of scalar and vector instructions to a first scalar pipeline;
assigning vector instructions of the set of scalar and vector instructions to a vector pipeline; and
initializing the kernel for execution.
14 . The system of claim 13 , wherein the set of scalar and vector instructions are configured to be executed in parallel.
15 . The system of claim 13 , further comprising prioritizing the assigned scalar instructions in the first scalar pipeline.
16 . The system of claim 15 , further comprising assigning a priority flag for the prioritized scalar instructions.
17 . The system of claim 13 , wherein the first scalar pipeline comprises a majority of scalar registers.
18 . The system of claim 13 , wherein the secondary scalar pipeline comprises a subset of scalar registers.