Quantum circuit optimization

1. A computer-implemented method of optimizing a quantum circuit, the method comprising:

identifying, from a first set of quantum circuit gates, a second set of quantum circuit gates that perform a predetermined function;

searching a library of templates stored on a non-transitory computer readable medium to find a template of quantum circuit gates that performs the predetermined function by compiling abstract gate operations into a set of hardware-specific operations that manipulate qubit states using qubit mapping and gate mapping to find a match, the gate mapping including matching a type and ordering of quantum circuit gates, defined over a graphical representation of the quantum circuit, between the quantum circuit and the template of quantum circuit gates; and

replacing the identified set of quantum circuit gates with the found template of quantum circuit gates,

wherein the method is executed in a pipeline in combination with a quantum circuit compilation and an additional quantum optimization.

2. The computer-implemented method of claim 1 , wherein the template of quantum circuit gates has a lower quantum cost than the identified set of quantum circuit gates.

3. The computer-implemented method of claim 2 , wherein the quantum cost of the identified quantum circuit gates and the quantum cost of the found template of quantum circuit gates are calculated using a same algorithm.

4. The computer-implemented method of claim 1 , wherein the templates in the library of templates are generated with parallel gates to modify circuit topology.

5. The computer-implemented method of claim 1 , wherein the method is performed automatically upon receiving the quantum circuit.

6. The computer-implemented method of claim 5 , wherein the method is performed in a serial manner.

7. The computer-implemented method of claim 5 , wherein the method is performed in a parallel manner.

8. A non-transitory computer-readable medium storing executable instructions that, upon execution, cause a digital computing processor, in a pipeline in combination with a quantum circuit compilation and an additional quantum optimization, to:

receive a quantum circuit;

identify, from within the received quantum circuit, a pattern of quantum gates that matches at least a part of at least one pattern from a pre-generated library of templates stored on a non-transitory computer readable medium coupled to the digital computing processor;

search the library of templates for a replacement pattern of quantum gates by compiling abstract gate operations into a set of hardware-specific operations that manipulate qubit states using qubit mapping and gate mapping to find a match, the gate mapping including matching a type and ordering of quantum gates, defined over a graphical representation of the quantum circuit, between the quantum circuit and the template of quantum circuit gates;

determine that a quantum cost of the replacement pattern of quantum gates is lower than a quantum cost of the identified pattern of quantum gates; and

replace the identified pattern of quantum gates with the replacement pattern of quantum gates.

9. The computer-readable medium of claim 8 , wherein the quantum cost of the identified pattern of quantum circuit gates and the quantum cost of the replacement pattern of quantum circuit gates are reduced by an abstract data structure.

10. The computer-readable medium of claim 9 , wherein the quantum cost of the identified pattern of quantum circuit gates and the quantum cost of the replacement pattern of quantum circuit gates are assigned respective values in accordance with a customizable cost function.

11. The computer-readable medium of claim 8 , wherein the replacement pattern of quantum circuit gates includes at least one quantum gate.

12. The computer-readable medium of claim 8 , wherein the identified pattern of quantum gates is replaced with an identity operation.

13. The computer-readable medium of claim 8 , wherein the digital computing processor searches the library at least partially on a GPU (graphics processing unit) and at least partially on a CPU (central processing unit).

14. An optimizer, comprising:

a circuit configured to analyze a quantum circuit to identify a pattern of quantum gates that matches at least a part of a pattern from a previously generated library of templates;

a library of templates stored on a non-transitory computer readable medium;

a processor configured to execute instructions that cause the processor, in a pipeline in combination with a quantum circuit compilation and an additional quantum optimization, to:

execute an algorithm to search for a replacement pattern of quantum gates,

identify the replacement pattern of quantum gates to replace the identified pattern of quantum gates, when a quantum cost of the replacement pattern of quantum gates is determined to be less than a quantum cost of the identified pattern of quantum gates by compiling abstract gate operations into a set of hardware-specific operations that manipulate qubit states using qubit mapping and gate mapping between the pattern of quantum gates and the replacement pattern of quantum gates to find the match, the gate mapping including matching a type and ordering of quantum gates, defined over a graphical representation of the quantum circuit, between the quantum circuit and the template of quantum circuit gates, and

replace the identified pattern of quantum gates with the replacement pattern of quantum gates.

15. The optimizer of claim 14 , wherein the library stores abstract data structures that respectively represent the quantum cost of the identified pattern of quantum circuit gates and the quantum cost of the replacement pattern of quantum circuit gates.

16. The optimizer of claim 14 , wherein the quantum cost of the identified pattern of quantum circuit gates and the quantum cost of the replacement pattern of quantum circuit gates are assigned respective values in accordance with a customizable cost function.

17. The optimizer of claim 14 , wherein properties of respective patterns of quantum gates are modifiable.

18. The optimizer of claim 14 , wherein the templates in the library of templates are generated with parallel gates to modify circuit topology.

19. The optimizer of claim 14 , wherein the templates in the library of templates are generated with parallel gates to reduce quantum circuit depth.