IP Library Granted Patent US 10,559,428
Granted Patent B2
US 10,559,428 · App. 16/281,825 · Granted Feb 11, 2020

Multilayer ceramic electronic component and method of manufacturing the same

Inventors: Hye Young Choi (Suwon-si, KR); Jae Yeol Choi (Suwon-si, KR); Hyun Hee Gu (Suwon-si, KR); Bum Su Kim (Suwon-si, KR)
Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
H01G4/30H01G4/232H01G4/12H01G4/2325
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Quick Facts
Patent No.
US 10,559,428
App. No.
16/281,825
Granted
Feb 11, 2020
Kind
B2
Abstract

A multilayer ceramic electronic component includes: a ceramic body including dielectric layers and internal electrodes; and external electrodes disposed on external surfaces of the ceramic body, wherein the external electrodes include seed layers disposed on at least one surface of the ceramic body in a thickness direction, first electrode layers electrically connected to the internal electrodes and the seed layers, and plating layers disposed on the seed layers and the first electrode layers, respectively, and 0.8≤T 2 /T 1 ≤1.2, where T 1 is a thickness of each of the first electrode layers in a central region of the ceramic body in the thickness direction, and T 2 is a thickness of each of the first electrode layers at a point at which an outermost internal electrode, among the internal electrodes, is positioned.

Claims (26)

1. A multilayer ceramic electronic component comprising:

a ceramic body including dielectric layers and internal electrodes stacked to be alternately exposed to a first end surface and a second end surface of the ceramic body with respective dielectric layers interposed therebetween; and

external electrodes disposed on external surfaces of the ceramic body,

wherein the external electrodes include seed layers disposed on at least one surface of the ceramic body in a thickness direction, first electrode layers electrically connected to the internal electrodes and the seed layers, and plating layers disposed on the seed layers and the first electrode layers, respectively,

0.8≤T 2 /T 1 ≤1.2, where T 1 is a thickness of each of the first electrode layers in a central region of the ceramic body in the thickness direction, and T 2 is a thickness of each of the first electrode layers at a point at which an outermost internal electrode, among the internal electrodes, is positioned, and

the first electrode layers are connected to the seed layers in contact portions between the at least one surface of the ceramic body in the thickness direction and the at least one surface of the ceramic body in a length direction,

wherein the first electrode layers and the seed layers directly contact each other without a gap.

2. The multilayer ceramic electronic component of claim 1 , wherein the first electrode layers and the seed layers are connected to each other in corner portions of the ceramic body.

3. The multilayer ceramic electronic component of claim 1 , wherein 0.4≤ T 3 /T 1 ≤1.0, where T 3 is a thickness of each of the first electrode layers in corner portions of the ceramic body.

4. The multilayer ceramic electronic component of claim 1 , wherein the first electrode layers are disposed on first and second end surfaces of the ceramic body in a length direction, respectively.

5. The multilayer ceramic electronic component of claim 1 , wherein the first electrode layers extend to portions of upper surfaces of the seed layers.

6. The multilayer ceramic electronic component of claim 1 , wherein the seed layers are only disposed on one surface of the ceramic body in the thickness direction.

7. The multilayer ceramic electronic component of claim 6 , wherein the one surface of the ceramic body in the thickness direction is a mounting surface of the multilayer ceramic electronic component mounted on a board.

8. The multilayer ceramic electronic component of claim 6 , wherein the plating layers are disposed on first and second end surfaces of the ceramic body in a length direction, and extend to the one surface of the ceramic body in the thickness direction.

9. A multilayer ceramic electronic component comprising:

a ceramic body in which a plurality of internal electrodes are stacked with respective dielectric layers interposed therebetween; and

external electrodes formed on surfaces of the ceramic body to be connected to the internal electrodes,

wherein the external electrodes include seed layers formed on at least one surface of the ceramic body in a thickness direction, first electrode layers electrically connected to the internal electrodes, and plating layers disposed on the seed layers and the first electrode layers,

the first electrode layers are formed on only end surfaces of the ceramic body in a length direction of the ceramic body, and

the first electrode layers and the seed layers directly contact each other without a gap.

10. The multilayer ceramic electronic component of claim 9 , wherein 0.8≤T 2 /T 1 ≤1.2, where T 1 is a thickness of each of the first electrode layers in a central region of the ceramic body in the thickness direction, and T 2 is a thickness of each of the first electrode layers at a point at which an outermost internal electrode, among the internal electrodes, is positioned.

11. The multilayer ceramic electronic component of claim 9 , wherein 0.4≤T 3 /T 1 ≤1.0, where T 3 is a thickness of each of the first electrode layers in corner portions of the ceramic body.

12. The multilayer ceramic electronic component of claim 9 , wherein the external electrodes are not formed on both surfaces of the ceramic body in the width direction of the ceramic body.

13. The multilayer ceramic electronic component of claim 9 , wherein the seed layers include first and second seed layers formed on a top surface of the ceramic body in the thickness direction, and third and fourth seed layers formed on a bottom surface of the ceramic body in the thickness direction,

the first and second seed layers are disposed at opposite ends of the top surface of the ceramic body in the thickness direction, and

the third and fourth seed layers are disposed at opposite ends of the bottom surface of the ceramic body in the thickness direction.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2019
From: CHOI, HYE YOUNG; CHOI, JAE YEOL; GU, HYUN HEE; KIM, BUM SU
To: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Reel/Frame 048400/0568 →
Priority Claims (1)
KR 10-2016-0041387 · Apr 5, 2016 · national
Continuity (2)
Continuation 15398264 · Jan 4, 2017
Related Publication 20190180941A1 · Jun 13, 2019