Monitoring potential of neuron circuits
A neuromorphic electric system includes a network of plural neuron circuits connected in series and in parallel to form plural layers. Each of the plural neuron circuits includes: a soma circuit that stores a charge supplied thereto and outputs a spike signal; and plural synapse circuits that supply a charge to the soma circuit according to a spike signal fed to the synapse circuits, a number of the plural synapse circuits being one more than a number of plural neuron circuits in a prior layer outputting the spike signal to the synapse circuits. One of the plural synapse circuits supplies a charge to the soma circuit in response to receiving a series of pulse signals, and the others of the plural synapse circuits supply a charge to the soma circuit in response to receiving a spike signal from corresponding neuron circuits in the prior layer.
1. A method for monitoring a neuron potential in a neuromorphic electric system including a network of a plurality of layers, the method comprising:
feeding test data to a plurality of input terminals of the plurality of layers in the neuromorphic electric system to cause the system to perform a normal operation; and
sending a series of pulse signals, after the normal operation, to a predetermined input terminal of the plurality of input terminals in each of the plurality of layers to determine a number of pulse signals at a time when the circuit connected to each of a plurality of output terminals fires, with the predetermined input terminal being unconnected to any one of the plurality of output terminals in the prior layer with a resistor element connected to the predetermined input terminal having a same resistance value as one of predetermined input terminals in each of the plurality of layers.
2. The method of claim 1 , further comprising changing a state of a switch in each of the plurality of layers to disable a leak function in at least one of the plurality of layers.
3. The method of claim 1 , further comprising changing a state of a switch in each of the plurality of layers to enable a leak function in at least one of the plurality of layers.
4. The method of claim 1 , further comprising setting a resistance value in the plurality of resistor elements connected to the predetermined input terminal higher than resistance values in the plurality of resistor elements connected to the plurality of general input terminals.
5. The method of claim 1 , further comprising setting a resistance value in the plurality of resistor elements connected to the predetermined input terminal lower than resistance values in the plurality of resistor elements connected to the plurality of general input terminals.
6. The method of claim 1 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data.
7. The method of claim 1 , wherein the series of pulse signals occur at a fixed interval.
8. The method of claim 1 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data, with the resistance values greater than a fixed resistance value set in a resistor element connected to the predetermined input terminal.
9. The method of claim 1 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data, with the resistance values less than a fixed resistance value set in a resistor element connected to the predetermined input terminal.
10. A method for monitoring a neuron potential in a neuromorphic electric system including a network of a plurality of layers, the method comprising:
setting a resistance value in a plurality of resistor elements;
feeding test data to a plurality of input terminals of the plurality of layers in the neuromorphic electric system to cause the system to perform a normal operation; and
sending a series of pulse signals, after the normal operation, to a predetermined input terminal of the plurality of input terminals in each of the plurality of layers to determine a number of pulse signals at a time when the circuit connected to each of a plurality of output terminals fires, with the predetermined input terminal being unconnected to any one of the plurality of output terminals in the prior layer with a resistor element connected to the predetermined input terminal having a same resistance value as one of predetermined input terminals in each of the plurality of layers.
11. The method of claim 10 , further comprising changing a state of a switch in each of the plurality of layers to disable a leak function in at least one of the plurality of layers.
12. The method of claim 10 , further comprising changing a state of a switch in each of the plurality of layers to enable a leak function in at least one of the plurality of layers.
13. The method of claim 10 , further comprising changing the resistance value in the plurality of resistor elements connected to the predetermined input terminal to be higher than the resistance values in the plurality of resistor elements connected to the plurality of general input terminals.
14. The method of claim 10 , further comprising changing the resistance value in the plurality of resistor elements connected to the predetermined input terminal to be lower than the resistance values in the plurality of resistor elements connected to the plurality of general input terminals.
15. The method of claim 10 , wherein feeding test data includes learning the resistance values in the plurality of resistor elements responsive to the test data.
16. The method of claim 10 , wherein the series of pulse signals occur at a fixed interval.
17. The method of claim 10 , wherein feeding test data includes learning the resistance values in the plurality of resistor elements responsive to the test data, with the resistance values greater than a fixed resistance value set in a resistor element connected to the predetermined input terminal.
18. The method of claim 10 , wherein feeding test data includes learning resistance values in the plurality of resistor elements responsive to the test data, with the resistance values less than a fixed resistance value set in a resistor element connected to the predetermined input terminal.