Semiconductor storage device
View Patent ↗A semiconductor storage device includes a first memory cell electrically connected to a first bit line and a first word line, a second memory cell electrically connected to a second bit line and the first word line, and a first circuit configured to supply voltages to the first word line. During a reading operation to read a page of memory cells including the first memory cell and the second memory cell, the first circuit supplies a first voltage to the first word line while the first memory cell is selected as a read target during a first time period, and supplies a second voltage greater than the first voltage to the first word line while the second memory cell is selected as a read target during a second time period that is different from the first time period, and directly thereafter, supplies the first voltage to the first word line.
1. A semiconductor storage device, comprising:
a first memory cell electrically connected to a first bit line and a first word line;
a second memory cell electrically connected to a second bit line and the first word line; and
a first circuit configured to supply voltages to the first word line, wherein
during a reading operation to read a page of memory cells including the first memory cell and the second memory cell, while the first memory cell is selected as a read target during a first time period, the first circuit supplies:
a first voltage to the first word line,
a second voltage less than the first voltage to the first word line after supplying the first voltage, and
a third voltage greater than the second voltage to the first word line after supplying the second voltage; and
during the reading operation to read the page of memory cells including the first memory cell and the second memory cell, while the second memory cell is selected as the read target during a second time period that is different from the first time period, the first circuit supplies:
the first voltage to the first word line,
a fourth voltage less than the second voltage to the first word line after supplying the first voltage,
the second voltage to the first word line after supplying the fourth voltage, and
a fifth voltage greater than the third voltage to the first word line after supplying the second voltage.
2. The semiconductor storage device according to claim 1 , wherein a distance from the first circuit to the first memory cell is shorter than a distance from the first circuit to the second memory cell.
3. The semiconductor storage device according to claim 1 , wherein during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies the second voltage to the first word line directly after supplying the fourth voltage.
4. The semiconductor storage device according to claim 3 , wherein during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies the third voltage to the first word line directly after supplying the fifth voltage.
5. The semiconductor storage device according to claim 4 , wherein
during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies:
the second voltage to the first word line directly after supplying the first voltage, and
the third voltage to the first word line directly after supplying the second voltage; and
during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:
the fourth voltage to the first word line directly after supplying the first voltage, and
the fifth voltage to the first word line directly after supplying the second voltage.
6. The semiconductor storage device according to claim 1 , further comprising:
a third memory cell electrically connected to a third bit line and the first word line, the third bit line being between the first bit line and the second bit line; and
a fourth memory cell electrically connected to a fourth bit line and the first word line, the second bit line being between the third bit line and the fourth bit line, wherein during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies:
a sixth voltage to the first bit line, and
a seventh voltage to the third bit line, the second bit line and the fourth bit line; and
during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:
the sixth voltage to the second bit line, and
the seventh voltage to the first bit line, the third bit line and the fourth bit line.
7. The semiconductor storage device according to claim 1 , wherein the first and second bit lines are adjacent.
8. The semiconductor storage device according to claim 1 , wherein the first memory cell is between the first circuit and the second memory cell along the first word line.
9. A semiconductor storage device, comprising:
a first memory cell electrically connected to a first bit line and a first word line;
a second memory cell electrically connected to a second bit line and the first word line; and
a first circuit configured to supply voltages to the first word line, wherein
during a reading operation to read a page of memory cells including the first memory cell and the second memory cell, while the first memory cell is selected as a read target during a first time period, the first circuit supplies:
a first voltage to the first word line,
a second voltage less than the first voltage to the first word line after supplying the first voltage, and
a third voltage less than the second voltage to the first word line directly after supplying the second voltage; and
during the reading operation to read the page of memory cells including the first memory cell and the second memory cell, while the second memory cell is selected as the read target during a second time period that is different from the first time period, the first circuit supplies:
the first voltage to the first word line,
a fourth voltage less than the second voltage to the first word line directly after supplying the first voltage,
the second voltage to the first word line directly after supplying the fourth voltage, and
a fifth voltage less than the third voltage to the first word line directly after supplying the second voltage.
10. The semiconductor storage device according to claim 9 , wherein a distance from the first circuit to the first memory cell is shorter than a distance from the first circuit to the second memory cell.
11. The semiconductor storage device according to claim 9 , wherein during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies the second voltage to the first word line directly after supplying the fourth voltage.
12. The semiconductor storage device according to claim 11 , wherein during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies the third voltage to the first word line directly after supplying the fifth voltage.
13. The semiconductor storage device according to claim 12 , wherein
during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies:
the second voltage to the first word line directly after supplying the first voltage, and
the third voltage to the first word line directly after supplying the second voltage; and
during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:
the fourth voltage to the first word line directly after supplying the first voltage, and
the fifth voltage to the first word line directly after supplying the second voltage.
14. The semiconductor storage device according to claim 9 , further comprising:
a third memory cell electrically connected to a third bit line and the first word line, the third bit line being between the first bit line and the second bit line; and
a fourth memory cell electrically connected to a fourth bit line and the first word line, the second bit line being between the third bit line and the fourth bit line, wherein
during the reading operation to read the page of the memory cells, while the first memory cell is selected as the read target during the first time period, the first circuit supplies:
a sixth voltage to the first bit line, and
a seventh voltage to the third bit line, the second bit line and the fourth bit line, and
during the reading operation to read the page of the memory cells, while the second memory cell is selected as the read target during the second time period, the first circuit supplies:
the sixth voltage to the second bit line, and
the seventh voltage to the first bit line, the third bit line and the fourth bit line.
15. The semiconductor storage device according to claim 9 , wherein the first and second bit lines are adjacent.
16. The semiconductor storage device according to claim 9 , wherein the first memory cell is between the first circuit and the second memory cell along the first word line.