IP Library Granted Patent US 10,536,301
Granted Patent B2
US 10,536,301 · App. 16/283,951 · Granted Jan 14, 2020

Methods and apparatus for an interface

Inventors: Athar Ali Khan. P (Kanaka Nagar, IN); Manish Kumar Viswkarma (Bangalore, IN)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H04L25/028H04L5/14H04L25/0292
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Quick Facts
Patent No.
US 10,536,301
App. No.
16/283,951
Granted
Jan 14, 2020
Kind
B2
Abstract

Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured as a low-voltage, bi-directional channel redriver having a transmitter and a receiver that share input pads and output pads. The interface may provide for selective biasing of the transmitter and receiver using a switching circuit and a resistance circuit connected to the channel's input and output pads.

Claims (87)

1. An interface circuit, comprising:

a receiver connected to a transmitter;

a first pair of I/O pads connected to:

an input of the receiver;

an output of the transmitter; and

a first resistance circuit;

a second pair of I/O pads connected to:

an output of the receiver;

an input of the transmitter; and

a second resistance circuit; and

at least one switching circuit connected to one of the first and second resistance circuits;

wherein the at least one switching circuit is connected to a plurality of voltages.

2. The interface circuit according to claim 1 , wherein each of the first and second resistance circuits comprises a plurality of resistors.

3. The interface circuit according to claim 1 , wherein each of the first and second switching circuits comprises a plurality of switching devices.

4. The interface circuit according to claim 1 , wherein:

the first resistance circuit is directly connected to:

a first I/O pad from the first pair of I/O pads; and

a second I/O pad from the first pair of I/O pads; and

the second resistance circuit is directly connected to:

a first I/O pad from the second pair of I/O pads; and

a second I/O pad from the second pair of I/O pads.

5. The interface circuit according to claim 1 , wherein each voltage from the plurality of voltages is less than 3.0 volts.

6. The interface circuit according to claim 1 , further comprising:

a first switching circuit connected to the first pair of I/O pads via the first resistance circuit; and

a second switching circuit connected to the second pair of I/O pads via the second resistance circuit;

wherein each switching circuit is:

connected to the plurality of voltages; and

selectively operable to apply:

a first voltage to the first pair of I/O pads; and

a second voltage to the second pair of I/O pads.

7. The interface circuit according to claim 6 , wherein:

the first switching circuit is configured to selectively connect a first voltage from the plurality of voltages to the first pair of I/O pads via the first resistance circuit; and

the second switching circuit is configured to selectively connect a second voltage from the plurality of voltages to the second pair of I/O pads via the second resistance circuit;

wherein the second voltage is different from the first voltage.

8. The interface circuit according to claim 7 , wherein:

the first resistance circuit comprises:

a first resistive element connected between a second I/O pad from the first pair of I/O pads and the first switching circuit; and

a second resistive element connected between a first I/O pad from the first pair of I/O pads and the first switching circuit; and

the second resistance circuit comprises:

a third resistive element connected between a first I/O pad from the second pair of I/O pads and the second switching circuit; and

a fourth resistive element connected between a second I/O pad from the second pair of I/O pads and the second switching circuit.

9. The interface circuit according to claim 1 , wherein:

the first resistance circuit comprises:

a first resistive element directly connected to a second I/O pad from the first pair of I/O pads; and

a second resistive element directly connected to a first I/O pad from the first pair of I/O pads; and

the second resistance circuit comprises:

a third resistive element directly connected to a first I/O pad from the second pair of I/O pads; and

a fourth resistive element directly connected to a second I/O pad from the second pair of I/O pads.

10. A method for operating an interface circuit, comprising:

during a first mode:

applying a first voltage to a first pair of I/O pads via a first resistance circuit;

applying a second voltage to a second pair of I/O pads via a second resistance circuit, wherein the second voltage is different from the first voltage; and

during a second mode:

applying the second voltage to the first pair of I/O pads via the first resistance circuit; and

applying the second voltage to the second pair of I/O pads via the second resistance circuit;

wherein:

the first resistance circuit comprises:

a first resistive element connected to a second I/O pad from the first pair of I/O pads; and

a second resistive element connected to a first I/O pad from the first pair of I/O pads; and

the second resistance circuit comprises:

a third resistive element connected to a first I/O pad from the second pair of I/O pads; and

a fourth resistive element connected to a second I/O pad from the second pair of I/O pads.

11. The method according to claim 10 , wherein applying the first voltage to the first pair of I/O pads comprises selectivity operating a first switching device connected to the first resistance circuit.

12. The method according to claim 10 , wherein applying the second voltage to the second pair of I/O pads comprises selectively operating a second switching device connected to the second resistance circuit.

13. The method according to claim 10 , wherein the interface is configured as a bi-directional channel comprising a transmitter connected to and in parallel with a receiver.

14. The method according to claim 10 , wherein the first and second voltages are less than 3.0 volts.

15. The method according to claim 10 , wherein the interface is configured as a uni-directional channel comprising one of: a transmitter and a receiver.

16. A system, comprising:

a host device connected to a sink device via an interface circuit, wherein the interface circuit comprises:

a bi-directional channel comprising:

a receiver;

a transmitter connected to the receiver;

a first pair of I/O pads shared by an input of the receiver and an output of the transmitter; and

a second pair of I/O pads shared by an output of the receiver and an input of the transmitter;

a first resistance circuit connected to the first pair of I/O pads;

a first switching circuit connected to the first resistance circuit and configured to selectively apply a first voltage to the first pair of I/O pads;

a second resistance circuit connected to the second pair of I/O pads; and

a second switching circuit connected to the second resistance circuit and configured to selectively apply a second voltage, which is different from the first voltage, to the second pair of I/O pads.

17. The system according to claim 16 , wherein:

the first resistance circuit comprises:

a first resistive element directly connected to a second I/O pad from the at least one pair of I/O pads; and

a second resistive element directly connected to a first I/O pad from the at least one pair of I/O pads.

18. The system according to claim 16 , wherein:

the first switching circuit is connected to a plurality of voltages;

the first switching device comprises a plurality of switching devices; and

each switching device from the plurality of switching devices connects one voltage from the plurality of voltages to the first resistance circuit.

19. The system according to claim 16 , wherein the host device is connected to the interface circuit via a first transmission line; and the sink device is connected to the interface via a second transmission line.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 25, 2019
From: KHAN. P, ATHAR ALI; VISWKARMA, MANISH KUMAR
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 048421/0428 →
Priority Claims (1)
IN 201811022324 · Jun 14, 2018 · national
Continuity (1)
Related Publication 20190386853A1 · Dec 19, 2019