IP Library Granted Patent US 10,811,514
Granted Patent B2
US 10,811,514 · App. 16/287,400 · Granted Oct 20, 2020

Electronic device including an enhancement-mode HEMT and a method of using the same

Inventors: Woochul Jeon (Scottsdale, AZ); Balaji Padmanabhan (Chandler, AZ)
Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
H01L29/66484H01L27/0605H01L29/2003H01L29/205H01L29/42316H01L29/66431H01L29/66462H01L29/66477H01L29/778H01L29/7786H01L29/7787H03K17/687
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Quick Facts
Patent No.
US 10,811,514
App. No.
16/287,400
Granted
Oct 20, 2020
Kind
B2
Abstract

An electronic device can include an enhancement-mode high electron mobility transistor (HEMT) that includes a source electrode; a drain electrode; and a gate. In an embodiment, the gate can correspond to spaced-apart gate electrodes and a space disposed between the spaced-apart gate electrodes, wherein the first space has a width configured such that, a continuous depletion region forms across all of the width of the first space. In another embodiment, the gate can be a gate electrode having a nonuniform thickness along a line in a gate width direction. In another aspect, a method of using the electronic device can include, during a transient period when the HEMT is in an off-state, flowing current from the drain electrode to the source electrode when Vds>−Vth+Vgs.

Claims (46)

1. An electronic device including an enhancement-mode high electron mobility transistor comprising:

a channel layer;

a barrier layer overlying the channel layer;

a source electrode;

a drain electrode; and

a gate corresponding to a first set of spaced-apart gate electrodes and a first space disposed between the spaced-apart gate electrodes, wherein:

the first set of spaced-apart gate electrodes and the first space are oriented along a first line in a width direction of the enhancement-mode high electron mobility transistor,

the first set of spaced-apart gate electrodes covers first portions of each of the channel layer and the barrier layer,

the first space covers a second portion of each of the channel layer and the barrier layer,

the first space has a width configured such that a continuous depletion region forms across all of the width of the first space.

2. The electronic device of claim 1 , further comprising a high-side transistor, wherein a source electrode of the high-side transistor is coupled to the drain electrode of the enhancement-mode high electron mobility transistor.

3. The electronic device of claim 1 , wherein the continuous depletion region separates a drain-side two-dimension electron gas from a source-side two dimension electron gas.

4. The electronic device of claim 1 , wherein at least one gate electrode within the first set of spaced-apart gate electrodes has a tapered or rounded corner.

5. The electronic device of claim 4 , wherein the tapered or rounded corner faces the drain electrode.

6. The electronic device of claim 1 , wherein the gate further comprises a second set of spaced-apart gate electrodes, wherein the second set of spaced-apart gate electrodes are oriented along a second line that is substantially parallel to and spaced apart from the first line.

7. The electronic device of claim 6 , wherein at least one gate electrode within the second set of spaced-apart gate electrodes has a tapered or rounded corner.

8. The electronic device of claim 7 , wherein none of the gate electrodes within the first set of spaced-apart gate electrodes has a tapered or rounded corner.

9. The electronic device of claim 7 , wherein the tapered or rounded corner faces the drain electrode.

10. The electronic device of claim 1 , wherein the enhancement-mode high electron mobility transistor further comprises:

a channel layer that includes GaN;

a barrier layer that includes Al x Ga (1-x) N, wherein 0.05≤x≤0.3; and

the spaced-apart gate electrodes include p-type GaN.

11. A method of using an electronic device comprising:

providing an enhancement-mode high electron mobility transistor that includes a drain electrode and a source electrode; and

during a transient period when the enhancement-mode high electron mobility transistor is in an off-state, flowing current from the drain electrode to the source electrode when Vds>−Vth+Vgs, where Vds is a drain-to-source voltage, Vth is a threshold voltage of the enhancement-mode high electron mobility transistor, and Vgs is a 12 gate-to-source voltage.

12. The method of claim 11 , wherein Vgs is in a range of −0.1 V to +0.1 V.

13. The method of claim 11 , wherein Vgs is lower than −2 V.

14. The method of claim 11 , further comprising providing a high-side transistor, wherein a source electrode of the high-side transistor is coupled to the drain electrode of the enhancement-mode high electron mobility transistor.

15. The method of claim 14 , further comprising turning off the high-side transistor before flowing current from the drain electrode to the source electrode of the enhancement-mode high electron mobility transistor.

16. The method of claim 14 , wherein:

providing the enhancement-mode high electron mobility transistor comprises providing the enhancement-mode high electron mobility transistor that includes spaced-apart gate electrodes and a space between the gate electrodes; and

when the enhancement-mode high electron mobility transistor is at steady state in the off-state, a depletion region associated with the spaced-apart gate electrodes is continuous across all of a width of the space.

17. The method of claim 16 , wherein during a transient period, when the enhancement-mode high electron mobility transistor is in the off-state, a depletion region becomes discontinuous at the space between the spaced-apart gate electrodes of the enhancement-mode high electron mobility transistor.

18. The method of claim 17 , wherein the transient period is between turning off the high-side transistor and reaching the steady state when the enhancement-mode high electron mobility transistor is in the off-state.

19. An electronic device including an enhancement-mode high electron mobility transistor comprising:

a source electrode;

a drain electrode; and

a gate corresponding to a first set of spaced-apart gate electrodes and a second set of spaced-apart gate electrodes,

wherein:

a first space is disposed between the spaced-apart gate electrodes within the first set of spaced-apart gate electrodes,

the first space has a width configured such that a continuous depletion region forms across all of the width of the first space,

the first set of spaced-apart gate electrodes are oriented along a first line,

the second set of spaced-apart gate electrodes are oriented along a second line that is substantially parallel to and spaced apart from the first line,

at least one gate electrode within the second set of spaced-apart gate electrodes has a tapered or rounded corner, and

none of the gate electrodes within the first set of spaced-apart gate electrodes has a tapered or rounded corner.

20. The electronic device of claim 19 , wherein the tapered or rounded corner faces the drain electrode.

Assignments (3)
RELEASE OF SECURITY INTEREST IN PATENTS PREVIOUSLY RECORDED AT REEL 049473, FRAME 0932 Recorded Aug 17, 2023
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
Reel/Frame 064618/0721 →
SECURITY INTEREST Recorded Jun 14, 2019
From: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC; FAIRCHILD SEMICONDUCTOR CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 049473/0932 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2019
From: JEON, WOOCHUL; PADMANABHAN, BALAJI
To: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Reel/Frame 048462/0728 →