High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
Described is a low power, high-density a 1T-1C (one transistor and one capacitor) memory bit-cell, wherein the capacitor comprises a pillar structure having ferroelectric material (perovskite, improper ferroelectric, or hexagonal ferroelectric) and conductive oxides as electrodes. In various embodiments, one layer of the conductive oxide electrode wraps around the pillar capacitor, and forms the outer electrode of the pillar capacitor. The core of the pillar capacitor can take various forms.
1. An apparatus comprising:
a transistor having a source, a drain, and a gate;
a word-line coupled to the gate;
a bit-line that extends in a first direction, the bit-line coupled to one of the source or drain of the transistor;
a plate-line that extends in the first direction; and
a capacitive structure coupled to one of the source or drain of the transistor through one or more vias, and to the plate-line, wherein the capacitive structure comprises:
a perovskite having an inverted u-shape;
a first conductive oxide inside a gap area of the inverted u-shape, wherein the first conductive oxide abuts inner sidewalls of the perovskite, wherein the first conductive oxide fully fills the gap area, wherein a portion of the first conductive oxide is coupled to one of the source or the drain of the transistor;
a second conductive oxide that abuts outer sidewalls of the perovskite, wherein a portion of the second conductive oxide is coupled to the plate-line;
an insulative material that abuts outer sidewalls of the second conductive oxide, wherein the insulative material includes an oxide of Al; and
a refractive intermetallic material that abuts the first conductive oxide and bottom surfaces of the inverted u-shape of the perovskite.
2. The apparatus of claim 1 , wherein the refractive intermetallic material is a first refractive intermetallic material, and wherein the capacitive structure comprises:
a second refractive intermetallic material that abuts a sidewall of the second conductive oxide.
3. The apparatus of claim 1 , wherein the insulative material further includes Ti.
4. The apparatus of claim 1 , wherein the transistor is one of a planar transistor or a non-planar transistor.
5. The apparatus of claim 1 , wherein the perovskite is doped with La or Lanthanides.
6. The apparatus of claim 2 , wherein the first refractive intermetallic material is a conductive material which includes one or more of: Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co.
7. The apparatus of claim 1 , wherein the transistor is positioned in a backend of a die, or wherein the transistor is positioned in a frontend of the die.
8. The apparatus of claim 1 , wherein the first or second conductive oxides include oxides of one or more of: Ir, Ru, Pd, Ps, or Re.
9. The apparatus of claim 1 , wherein the perovskite includes one of: LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.
10. The apparatus of claim 1 , wherein the perovskite includes one of: La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.
11. The apparatus of claim 1 , wherein the capacitive structure is cylindrical in shape.
12. The apparatus of claim 1 , wherein the perovskite is doped with Sc or Mn to control leakage through the second conductive oxide.
13. A method for forming a memory bit-cell, the method comprising:
forming a transistor having a source, a drain, and a gate;
forming a word-line coupled to the gate;
forming a bit-line extending in a first direction, the bit-line coupled to one of the source or drain of the transistor; forming a plate-line extending in the first direction; and
forming a capacitive structure coupled to one of the source or drain of the transistor through one or more vias, wherein forming the capacitive structure comprises:
forming a perovskite having an inverted u-shape;
forming a first conductive oxide inside a gap area of the inverted u-shape, wherein the first conductive oxide fully fills the gap area, wherein a portion of the first conductive oxide is coupled to one of the source or the drain of the transistor;
forming a second conductive oxide abutting outer sidewalls of the perovskite, wherein a portion of the second conductive oxide is coupled to the plate-line;
forming an insulative material abutting outer sidewalls of the second conductive oxide, wherein the insulative material includes an oxide of Al; and
forming a refractive intermetallic material that abuts the first conductive oxide and bottom surfaces of the inverted u-shape of the perovskite.
14. The method of claim 13 , wherein the refractive intermetallic material is a first refractive intermetallic material, and wherein forming the capacitive structure comprises:
forming a second refractive intermetallic material abutting a sidewall of the second conductive oxide.
15. The method of claim 14 , wherein:
the insulative material includes Ti;
the transistor is one of a planar or non-planar transistor;
the perovskite is doped with La or Lanthanides;
the first refractive intermetallic material includes one or more of: Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co; and
the transistor is positioned in a backend of a die, or wherein the transistor is positioned in a frontend of the die.
16. The method of claim 13 , wherein the first or second conductive oxides include oxides of one or more of: Ir, Ru, Pd, Ps, or Re.
17. The method of claim 13 , wherein the perovskite includes one of: LaCoO3, SrCoO3, SrRuO3, LaMnO3, SrMnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.
18. The method of claim 13 , wherein the perovskite includes one of: La, Sr, Co, Ru, Mn, Y, Na, Cu, or Ni.
19. The method of claim 13 , wherein the capacitive structure is cylindrical in shape.
20. The method of claim 13 , wherein the perovskite is doped with Sc or Mn to control leakage through the second conductive oxide.
21. A system comprising:
an artificial intelligence processor; and
a non-volatile memory coupled to the artificial intelligence processor,
wherein the non-volatile memory includes bit cells, wherein one of the bit cells includes:
a transistor having a source, a drain, and a gate;
a word-line coupled to the gate;
a bit-line that extends in a first direction, the bit-line coupled to one of the source or drain of the transistor;
a plate-line that extends in the first direction; and a capacitive structure coupled to one of the source or drain of the transistor through one or more vias, and to the plate-line,
wherein the capacitive structure comprises:
a perovskite having an inverted u-shape;
a first conductive oxide inside a gap area of the inverted u-shape, wherein the first conductive oxide abuts inner sidewalls of the perovskite, wherein the first conductive oxide fully fills the gap area, wherein a portion of the first conductive oxide is coupled to one of the source or the drain of the transistor;
a second conductive oxide that abuts outer sidewalls of the perovskite, wherein a portion of the second conductive oxide is coupled to the plate-line;
an insulative material that abuts outer sidewalls of the second conductive oxide, wherein the insulative material includes an oxide of Al; and
a refractive intermetallic material that abuts the first conductive oxide and bottom surfaces of the inverted u-shape of the perovskite.
22. The system of claim 21 , wherein the refractive intermetallic material is a first refractive intermetallic material, and wherein the capacitive structure comprises:
a second refractive intermetallic material that abuts a sidewall of the second conductive oxide.
23. The system of claim 21 , wherein:
the insulative material further includes Ti;
the transistor is one of a planar or non-planar transistor;
the perovskite is doped with La or Lanthanides;
the first refractive intermetallic material includes one or more of: Ti, V, Cr, Mn, Zr, Nb, Mo, Tc, Ru, Rh, Hf, Ta, W, Re, Os, Ir, Al, or Co; and
the transistor is positioned in a backend of a die, or wherein the transistor is positioned in a frontend of the die.
24. The apparatus of claim 1 , wherein the insulative material has a lattice parameter which is substantially matched with a lattice parameter of the first conductive oxide.