Systems and methods for delta-sigma digitization
A baseband processing unit includes a baseband processor configured to receive a plurality of component carriers of a radio access technology wireless service, and a delta-sigma digitization interface configured to digitize at least one carrier signal of the plurality of component carriers into a digitized bit stream, for transport over a transport medium, by (i) oversampling the at least one carrier signal, (ii) quantizing the oversampled carrier signal into the digitized bit stream using two or fewer quantization bits.
1. A delta-sigma digitization system for modulating an input analog signal into a digitized bit stream, comprising:
a sampling unit configured to sample the input analog signal at a predetermined sampling rate to produce a sampled analog signal;
a delta-sigma analog-to-digital converter (ADC) configured to quantize the sampled analog signal into the digitized bit stream according to a predetermined number of quantization bits;
an output port for transmitting the digitized bit stream to a transport medium;
an input de-serializer configured to de-serialize the sampled analog signal into a plurality of separate pipelines; and
an output serializer configured to serialize the separate pipelines into the digitized bit stream at the output port.
2. The system of claim 1 , wherein the delta-sigma ADC comprises a field programmable gate array (FPGA).
3. The system of claim 2 , wherein the predetermined number of quantization bits is one, and wherein the delta-sigma ADC is further configured to perform one-bit quantization according to a binary quantization format.
4. The system of claim 3 , wherein the binary quantization format comprises on-off keying.
5. The system of claim 2 , wherein the sampling unit comprises an FPGA mezzanine card (FMC).
6. The system of claim 5 , wherein the FMC is configured to sample the input analog signal at 5 GSa/s.
7. The system of claim 1 , wherein an operational speed of each pipeline of the plurality of separate pipelines is approximately 156.25 MSa/s.
8. The system of claim 5 , wherein the output port comprises a multi-gigabit transceiver.
9. The system of claim 2 , wherein the delta-sigma ADC is disposed within a distributed unit (DU) of a communication network.
10. The system of claim 9 , wherein the DU comprises a baseband processing unit of a fronthaul segment of the communication network.
11. The system of claim 1 , wherein the input analog signal comprises at least one of a 5G new radio (5GNR) signal and a long term evolution (LTE) signal.
12. The system of claim 11 , wherein the input analog signal comprises at least one of a 64 QAM, a 256 QAM, and a 1024 QAM modulation format.