IP Library Granted Patent US 10,831,219
Granted Patent B2
US 10,831,219 · App. 16/289,189 · Granted Nov 10, 2020

Voltage regulator

Inventors: Tsutomu Tomioka (Chiba, JP); Tadakatsu Kuroda (Chiba, JP); Masakazu Sugiura (Chiba, JP)
Assignee: ABLIC INC.
G05F1/573H02H1/0007H02H9/02H02H9/025H03K17/0822
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Quick Facts
Patent No.
US 10,831,219
App. No.
16/289,189
Granted
Nov 10, 2020
Kind
B2
Abstract

A voltage regulator includes an error amplifier circuit which controls a gate voltage of an output transistor, an overcurrent protection circuit which prevents an overcurrent of the output transistor, and a protection circuit which detects a negative voltage of an output terminal and controls a gate voltage of the output transistor to suppress an overcurrent. The protection circuit includes a MOS transistor which controls the gate voltage of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor constructed from an N-type region connected to the output terminal as an emitter, a P-type substrate as a base, and the N-type region of the semiconductor element as a collector.

Claims (10)

1. A voltage regulator, comprising:

an error amplifier circuit configured to control a gate voltage of an output transistor with a voltage obtained by amplifying a difference between a voltage based on an output voltage supplied to an output terminal from the output transistor and a reference voltage;

an overcurrent protection circuit configured to detect an overcurrent of the output transistor and control the gate voltage of the output transistor to prevent the overcurrent; and

a protection circuit configured to detect a negative voltage of the output terminal and control the gate voltage of the output transistor to suppress an overcurrent, the protection circuit comprising a MOS transistor configured to control the gate of the output transistor, a clamp circuit connected to a gate of the MOS transistor, a semiconductor element having an N-type region connected to the clamp circuit, and a parasitic bipolar transistor in which an N-type region connected to the output terminal serves as an emitter, a P-type substrate serves as a base, and the N-type region of the semiconductor element serves as a collector.

2. The voltage regulator according to claim 1 , wherein the N-type region connected to the output terminal is an N-type region of a protection element.

3. The voltage regulator according to claim 2 , wherein the clamp circuit is a resistor, a current source or a diode-connected MOS transistor.

4. The voltage regulator according to claim 3 , wherein the semiconductor element having the N-type region is a diode or a transistor.

5. The voltage regulator according to claim 2 , wherein the semiconductor element having the N-type region is a diode or a transistor.

6. The voltage regulator according to claim 1 , wherein the clamp circuit is a resistor, a current source or a diode-connected MOS transistor.

7. The voltage regulator according to claim 1 , wherein the semiconductor element having the N-type region is a diode or a transistor.

Assignments (2)
CHANGE OF ADDRESS Recorded Jun 8, 2023
From: ABLIC INC.
To: ABLIC INC.
Reel/Frame 064021/0575 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 28, 2019
From: TOMIOKA, TSUTOMU; KURODA, TADAKATSU; SUGIURA, MASAKAZU
To: ABLIC INC.
Reel/Frame 048473/0481 →
Cited By (1)
US 12,468,326