IP Library Granted Patent US 12,468,326
Granted Patent B2
US 12,468,326 · App. 18/464,522 · Granted Nov 11, 2025

Voltage regulator

Inventors: Atsushi Haruyama (Nagano, JP); Yasuhiko Ogura (Nagano, JP); Teruo Suzuki (Nagano, JP)
Assignee: ABLIC INC.
G05F1/565G05F1/56G05F1/575
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Quick Facts
Patent No.
US 12,468,326
App. No.
18/464,522
Granted
Nov 11, 2025
Kind
B2
Abstract

Provided is a voltage regulator capable of suppressing a current consumption in a non-regulation state with a simple circuit configuration. The voltage regulator includes an output transistor supplying an output voltage based on a control voltage, an error amplifier circuit supplying an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage, a common source amplifier circuit supplying the control voltage to the output transistor based on the amplified signal, and a non-regulation state detection circuit supplying a detection signal to the common source amplifier circuit. The common source amplifier circuit includes a current control circuit including a plurality of parallel paths connecting between a control terminal of the output transistor and a power supply terminal, the plurality of parallel paths including a path to be closed in the non-regulation state and a path to be opened in the non-regulation state.

Claims (53)

1 . A voltage regulator, comprising:

an output transistor including a control terminal, and being configured to receive a control voltage from the control terminal and supply an output voltage;

an error amplifier circuit configured to supply an amplified signal obtained by amplifying a difference between a voltage based on the output voltage and a reference voltage;

a common source amplifier circuit configured to receive the amplified signal, and to supply the control voltage to the control terminal; and

a non-regulation state detection circuit configured to supply a detection signal including a signal level corresponding to one of a regulation state or a non-regulation state to the common source amplifier circuit,

the common source amplifier circuit including a current control circuit including a plurality of parallel paths each connecting between the control terminal of the output transistor and a first power supply terminal for supplying a first power supply voltage, the parallel paths including a first path to be a closed state in the non-regulation state and a second path to be an opened state in the non-regulation state.

2 . The voltage regulator according to claim 1 ,

wherein the current control circuit includes:

a plurality of current control transistors each provided in one of the plurality of parallel paths, and each including a first terminal connected to the control terminal of the output transistor, a control terminal for receiving the amplified signal, and a second terminal; and

a pass transistor including a first terminal connected to the second terminal of one of the plurality of current control transistors provided in the second path, a second terminal connected to the first power supply terminal, and a control terminal for receiving the detection signal, and being switchable to any one of the opened state or the closed state in accordance with the signal level of the detection signal, and

wherein the pass transistor is switched to the opened state in the non-regulation state.

3 . The voltage regulator according to claim 2 , wherein the second path includes two or more paths in parallel.

4 . The voltage regulator according to claim 2 ,

wherein the parallel paths include the second path and a third path to be switched to the opened state in the non-regulation state, and

wherein the second terminal of one of the plurality of current control transistors provided in the second path and the second terminal of one of the plurality of current control transistors provided in the third path are connected to each other.

5 . The voltage regulator according to claim 1 ,

wherein the current control circuit further includes a third path to be switched to the opened state in the non-regulation state,

wherein the current control circuit includes:

a plurality of current control transistors each provided in one of the plurality of parallel paths, and each including a first terminal connected to the control terminal of the output transistor, a control terminal for receiving the amplified signal, and a second terminal;

a first pass transistor including a first terminal connected to the second terminal of one of the plurality of current control transistors provided in the second path, a second terminal connected to the first power supply terminal, and a control terminal for receiving the detection signal, and being switchable to any one of the opened state or the closed state in accordance with the signal level of the detection signal; and

a second pass transistor including a first terminal connected to the second terminal of one of the plurality of current control transistors provided in the third path, a second terminal connected to the first power supply terminal, and a control terminal for receiving the detection signal, and being switchable to any one of the opened state or the closed state in accordance with the signal level of the detection signal, and

wherein the first pass transistor and the second pass transistor are switched to the opened state in the non-regulation state.

6 . The voltage regulator according to claim 1 ,

wherein the current control circuit includes:

a plurality of current control transistors connected in parallel between the control terminal of the output transistor and the first power supply terminal, and each including a control terminal for receiving the amplified signal; and

a switching circuit configured to switch between, in accordance with the signal level of the detection signal, an opened state in which the control terminal of one of the plurality of current control transistors provided in the second path and the error amplifier circuit are disconnected and a closed state in which the control terminal of the one of the plurality of current control transistors provided in the second path and the error amplifier circuit are connected, and

wherein the switching circuit is switched to the opened state in the non-regulation state.

7 . The voltage regulator according to claim 6 ,

wherein the switching circuit is configured to switch a connection destination of the control terminal of the one of the plurality of current control transistors provided in the second path, and

wherein, in the closed state, the connection destination is switched to the error amplifier circuit, and in the opened state, the connection destination is switched to the first power supply terminal.

8 . The voltage regulator according to claim 6 , wherein the switching circuit includes:

a first end connected to the error amplifier circuit;

a second end connected to the control terminal of the one of the plurality of current control transistors provided in the second path;

a control end for receiving the detection signal;

a first transistor pair being a pair of a first PMOS transistor and a first NMOS transistor, and including a first end connected to the first end of the switching circuit and a second end connected to the second end of the switching circuit;

a second transistor pair being a pair of a second PMOS transistor and a second NMOS transistor, and including a first end connected to the first power supply terminal and a second end connected to the second end of the switching circuit and the second end of the first transistor pair;

a first inverter for connecting between a gate of the first PMOS transistor and a gate of the first NMOS transistor; and

a second inverter for connecting a gate of the second PMOS transistor and a gate of the second NMOS transistor.

9 . The voltage regulator according to claim 7 , wherein the switching circuit includes:

a first end connected to the error amplifier circuit;

a second end connected to the control terminal of the one of the plurality of current control transistors provided in the second path;

a control end for receiving the detection signal;

a first transistor pair being a pair of a first PMOS transistor and a first NMOS transistor, and including a first end connected to the first end of the switching circuit and a second end connected to the second end of the switching circuit;

a second transistor pair being a pair of a second PMOS transistor and a second NMOS transistor, and including a first end connected to the first power supply terminal and a second end connected to the second end of the switching circuit and the second end of the first transistor pair;

a first inverter for connecting between a gate of the first PMOS transistor and a gate of the first NMOS transistor; and

a second inverter for connecting a gate of the second PMOS transistor and a gate of the second NMOS transistor.

10 . The voltage regulator according to claim 1 ,

wherein the current control circuit includes a plurality of current control transistors each provided in one of the plurality of parallel paths, and each including a first terminal connected to the control terminal of the output transistor, a control terminal for receiving the amplified signal, and a second terminal, and

wherein the common source amplifier circuit includes a current-voltage conversion circuit including a first port connected to a second power supply terminal for supplying a second power supply voltage, and a second port connected to the first terminal of each of the plurality of current control transistors and the control terminal of the output transistor.

11 . The voltage regulator according to claim 1 ,

wherein the current control circuit includes a plurality of transistors each provided in one of the plurality of paths connecting between the control terminal of the output transistor and the first power supply terminal in parallel, the plurality of transistors including a first transistor configured to switch between a conductive state and a non-conductive state, the first transistor being the conductive state during the regulation state and the non-conductive state during the non-regulation state, and a second transistor configured to be the conductive state regardless of whether the regulation state or the non-regulation state, wherein the first and the second transistors each contain a first terminal connected to the control terminal of the control transistor, a control terminal for receiving the amplified signal and a second terminal.

12 . The voltage regulator according to claim 1 ,

wherein the second path is configured to switch between the opened state and the closed state in accordance with the signal level of the detection signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 13, 2023
From: HARUYAMA, ATSUSHI; OGURA, YASUHIKO; SUZUKI, TERUO
To: ABLIC INC.
Reel/Frame 064884/0788 →
Priority Claims (1)
JP 2022-156544 · Sep 29, 2022 · national
Continuity (1)
Related Publication 20240111320A1 · Apr 4, 2024
References Cited (5)
US 10831219B2 · Tomioka · 2020 [cited by examiner]
US 20080265852A1 · Imura · 2008 [cited by examiner]
US 20100207591A1 · Imura · 2010 [cited by examiner]
US 20160349776A1 · Conte · 2016 [cited by examiner]
US 20200278710A1 · Sankman et al. · 2020 [cited by applicant]