Machine perception and dense algorithm integrated circuit

1. An integrated circuit comprising:

a plurality of array cores, each array core of the plurality of array cores comprising:

a plurality of distinct data processing circuits; and

a data queue register file;

a plurality of border cores, each border core of the plurality of border cores comprising:

at least a register file,

wherein:

[i] at least a subset of the plurality of border cores encompasses a periphery of a first subset of the plurality of array cores; and

[ii] a combination of the plurality of array cores and the plurality of border cores define an integrated circuit array.

2. The integrated circuit according to claim 1 , wherein

the first subset of the plurality of array cores encompasses a periphery of a second subset of the plurality of array cores.

3. The integrated circuit according to claim 1 , wherein

the plurality of distinct processing circuits of each of the plurality of array cores comprises:

a plurality of multiply accumulators, each of the plurality of multiply accumulators being arranged adjacent a data input/output port of a respective array core of the plurality of array cores.

4. The integrated circuit according to claim 1 , further comprising:

a first plurality of dual FIFOs that loads data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the first plurality of dual FIFOs is first disposed by the respective dual FIFO,

wherein the first plurality of dual FIFOs are arranged along a first peripheral side of the integrated circuit array;

a second plurality of dual FIFOs that loads data into the integrated circuit array on a first-in, first-out basis, such that an oldest dataset entering a respective dual FIFO of the second plurality of dual FIFOs is first disposed by the respective dual FIFO,

wherein the second plurality of dual FIFOs are arranged along a second peripheral side of the integrated circuit array that is distinct from the first peripheral side of the integrated circuit array.

5. The integrated circuit according to claim 4 , wherein:

each of the first and the second plurality of dual FIFOs comprise at least two memory elements;

a first of the at least two memory elements pushes data into one of a border core of the plurality of border cores and an array core of the plurality of array cores of the integrated circuit array;

a second of the at least two memory elements collects data from the one of a border core of the plurality of border cores and an array core of the plurality of array cores of the integrated circuit array.

6. The integrated circuit according to claim 3 , wherein:

each of the plurality of array cores having a rectangular shape; and

one of the plurality of multiply accumulators being arranged within the rectangular shape of each of the plurality of array cores.

7. The integrated circuit according to claim 1 , further comprising:

a first periphery memory and a second periphery memory that interface with unified memory, wherein:

the first periphery memory is arranged along a first peripheral side of the integrated circuit array and interfaces with a first periphery load store; and

the second periphery memory is arranged along a second peripheral side of the integrated circuit array and interfaces with a second periphery load store.

8. The integrated circuit according to claim 1 , further comprising:

a hierarchical memory structure that enables direct memory access between a main memory and the integrated circuit array, the hierarchical memory structure includes:

a plurality of dual FIFOs that interfaces with the integrated circuit array and transmits and accepts data on a first-in, first-out basis,

a plurality of periphery load stores that each interface with a respective dual FIFO of the plurality of dual FIFOs and store one or more loads of data that is either received from the respective dual FIFO and/or that is pending a loading into the respective dual FIFO, and

a plurality of periphery memory that each interface with a respective periphery load store of the plurality of periphery load stores and interfaces with the main memory.

9. The integrated circuit according to claim 8 , further comprising:

a plurality of periphery controllers that, when executing data movement instructions, control a movement of data between the hierarchical memory structure and the integrated circuit array.

10. The integrated circuit according to claim 8 , wherein

the hierarchical memory structure may be implemented as a two-dimensional direct memory access enabling data access and data reshaping during data transfers.

11. The integrated circuit according to claim 1 , further comprising:

a dispatch controller that provides:

(i) data movement instructions that causes an automatic movement of data: (a) between a hierarchical memory structure of the integrated circuit and the integrated circuit array; (b) within each respective array core of the plurality of array cores; (c) between respective array cores and between array cores and border cores of the integrated circuit array; and

(ii) computation instructions that defines a plurality of computations to be executed by the plurality of array cores of the integrated circuit array.

12. The integrated circuit according to claim 1 , further comprising:

a dispatch controller that provides data movement instructions, wherein the data movement instructions comprise a data flow schedule that:

(i) defines an automatic movement of data within the integrated circuits; and

(ii) sets one or more border cores of the plurality of border cores to a predetermined constant value if no data is provided to the one or more border cores according to the predetermined data flow schedule.

13. The integrated circuit according to claim 11 , wherein

the data flow schedule comprises a schedule of memory address executable by one or more of a plurality of periphery load stores.

14. The integrated circuit according to claim 1 , further comprising:

a dispatch controller comprising:

a compute instructions generator circuit that provides computation instructions for each of the plurality of array cores; and

a data movement generator circuit that provides a data flow schedule that defines predetermined movements of data within the integrated circuit.

15. The integrated circuit according to claim 1 , further comprising:

a broadcast bus arranged in electrical communication with one or more periphery controllers at a first input terminal of the broadcast bus and in electrical communication with a subset of the plurality of array cores at a plurality of output terminals of the broadcast bus.

16. The integrated circuit according to claim 1 , wherein

each of the plurality of array cores is arranged in bi-directional communication with a neighboring core that includes one or more of the plurality array cores and the plurality of border cores.

17. The integrated circuit according to claim 1 , wherein

each of the plurality of array cores further comprises at least one arithmetic logic unit.