Nanosheet transistor barrier for electrically isolating the substrate from the source or drain regions
Embodiments of the invention are directed to a nanosheet field effect transistor (FET) device. A non-limiting example of the nanosheet FET device includes a stack of channel nanosheets over a substrate, along with a source or drain (S/D) trench in a predetermined region of the substrate. The predetermined region of the substrate includes a region over which a S/D region of the nanosheet FET is formed. The S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets. An isolation barrier is formed in the S/D trench. The isolation barrier is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
1. A method of fabricating a nanosheet field effect transistor (FET), the method comprising:
forming a stack of channel nanosheets over a substrate;
forming a source or drain (S/D) trench in a predetermined region of the substrate;
wherein the predetermined region of the substrate comprises a region over which a S/D region of the nanosheet FET will be formed;
wherein the S/D region of the nanosheet FET will be formed at ends of a bottommost one of the stack of channel nanosheets; and
forming an isolation barrier in the S/D trench;
wherein the isolation barrier comprises a doped semiconductor material and is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
2. The method of claim 1 , wherein:
the doped semiconductor material comprises positively charged majority carriers; and
the S/D region will comprise negatively charged majority carriers.
3. The method of claim 1 , wherein:
the doped semiconductor material comprises negatively charged majority carriers; and
the S/D region will comprise positively charged majority carriers.
4. The method of claim 1 , wherein forming the isolation barrier comprises forming the doped semiconductor material in the S/D trench.
5. The method of claim 4 , wherein forming the doped semiconductor material comprises epitaxially growing the doped semiconductor material in the S/D trench.
6. The method of claim 5 , wherein:
the doped semiconductor material comprises positively charged majority carriers; and
the S/D region will comprise negatively charged majority carriers.
7. The method of claim 5 , wherein:
the doped semiconductor material comprises negatively charged majority carriers; and
the S/D region will comprise positively charged majority carriers.
8. The method of claim 1 , wherein forming the isolation barrier comprises implanting dopants through sidewalls of the S/D trench.
9. The method of claim 1 , wherein sidewalls of the S/D trench comprise (111) facets.
10. A nanosheet field effect transistor (FET) device comprising:
a stack of channel nanosheets over a substrate;
a source or drain (S/D) trench in a predetermined region of the substrate;
wherein the predetermined region of the substrate comprises a region over which a S/D region of the nanosheet FET is formed;
wherein the S/D region of the nanosheet FET is formed at ends of a bottommost one of the stack of channel nanosheets; and
an isolation barrier in the S/D trench;
wherein the isolation barrier comprises a doped semiconductor material and is configured to substantially prevent the S/D region from being electrically coupled to the substrate.
11. The device of claim 10 , wherein:
the doped semiconductor material comprises positively charged majority carriers; and
the S/D region will comprise negatively charged majority carriers.
12. The device of claim 10 , wherein:
the doped semiconductor material comprises negatively charged majority carriers; and
the S/D region will comprise positively charged majority carriers.
13. The device of claim 10 , wherein the isolation barrier comprises the doped semiconductor material in the S/D trench.
14. The device of claim 13 , wherein the doped semiconductor material comprises epitaxially grown doped semiconductor material.
15. The device of claim 14 , wherein:
the doped semiconductor material comprises positively charged majority carriers; and
the S/D region will comprise negatively charged majority carriers.
16. The device of claim 14 , wherein:
the doped semiconductor material comprises negatively charged majority carriers; and
the S/D region will comprise positively charged majority carriers.
17. The device of claim 10 , wherein the isolation barrier comprises a layer of dopants implanted through sidewalls of the S/D trench.
18. The device of claim 10 , wherein sidewalls of the S/D trench comprise (111) facets.