Stacked access device and resistive memory
A semiconductor device including stacked access device and resistive memory includes a stack disposed on a base structure, the stack including an access device stack and a resistive random-access memory (ReRAM) device stack, sidewall spacers disposed along a portion of the stack, a dielectric layer disposed over the stack, the sidewall spacers and the base structure, and an interlevel dielectric disposed on the dielectric layer.
1. A method for fabricating a semiconductor device including a stacked memory device, comprising:
forming a stack on a base structure, the stack including an access device stack disposed in direct contact with a resistive random-access memory (ReRAM) device stack, and a mask disposed on the access device stack, wherein the base structure includes a bottom electrode layer, the ReRAM device stack includes a middle electrode layer, and the access device stack includes a top electrode layer disposed in direct contact with a mixed ionic-electronic conductor (MIEC) layer, with the MIEC layer including at least sulfur directly contacting the middle electrode layer of the ReRAM stack;
patterning the access device stack using the mask to form a patterned access device stack on the ReRAM device stack;
forming a first dielectric layer over the patterned access device stack;
creating sidewall spacers disposed along the patterned access device stack from the first dielectric layer;
removing the mask by patterning the ReRAM device stack to form a patterned stack including a patterned ReRAM device stack and the patterned access device stack; and
conformally depositing a second dielectric layer over the patterned stack, the sidewall spacers and the base structure.
2. The method of claim 1 , further comprising forming an interlayer dielectric over the second dielectric layer.
3. The method of claim 2 , wherein:
the middle electrode layer is disposed on a metal oxide layer.
4. The method of claim 3 , further comprising forming the base structure, including:
depositing a third dielectric layer on a substrate;
patterning the third dielectric layer to create an opening within the third dielectric layer; and
forming the bottom electrode layer on the substrate in the opening.
5. The method of claim 3 , further comprising planarizing the interlayer dielectric and the second dielectric layer to the top electrode layer.
6. The method of claim 3 , further comprising forming a via contacting the top electrode layer through the interlayer dielectric and the second dielectric layer.