Semiconductor package

1. A semiconductor package, comprising:

a semiconductor chip on which a connection pad is disposed, and including a passivation film having a first opening exposing at least a portion of the connection pad and a protective film disposed on the passivation film, filling at least a first portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening;

an encapsulant covering at least a portion of the semiconductor chip; and

a connection structure disposed on an active surface of the semiconductor chip, and including a connection via connected to the connection pad in the first opening and the second opening and a redistribution layer electrically connected to the connection pad through the connection via,

wherein the second opening has a width narrower than a width of the first opening, and

wherein the connection structure includes an insulating layer disposed on the active surface of the semiconductor chip, the insulating layer filling at least a second portion of the first opening.

2. The semiconductor package of claim 1 , wherein a region, excluding a region exposed by the second opening, of a region exposed by the first opening of the connection pad, is covered by the protective film.

3. The semiconductor package of claim 1 , wherein the passivation film and the protective film are disposed in a region inside the active surface.

4. The semiconductor package of claim 3 , wherein the encapsulant covers a side surface of each of the passivation film and the protective film.

5. The semiconductor package of claim 3 , wherein the encapsulant fills a portion between the protective film and the connection structure.

6. The semiconductor package of claim 1 , wherein the insulating layer has a via hole connected to the second opening to expose at least a portion of the connection pad, the redistribution layer being disposed on the insulating layer, and the connection via electrically connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening.

7. The semiconductor package of claim 6 , wherein the insulating layer fills at least a portion of a space between the protective film and the connection via in the first opening.

8. The semiconductor package of claim 6 , wherein the insulating layer is physically spaced apart from the connection pad.

9. The semiconductor package of claim 6 , wherein the connection via includes a seed layer disposed on an exposed surface of the connection pad, a wall surface of the via hole, and a wall surface of the second opening, and a plating layer disposed on the seed layer and filling the via hole and the second opening.

10. The semiconductor package of claim 1 , wherein the protective film has a round shape having an inclination in the first opening.

11. The semiconductor package of claim 1 , wherein the protective film has a thickness thinner than a thickness of the passivation film.

12. The semiconductor package of claim 1 , further comprising: a frame having a through-hole,

wherein the semiconductor chip is disposed in the through-hole,

the encapsulant covers at least a portion of the frame, and

the encapsulant fills at least a portion of the through-hole.

13. The semiconductor package of claim 12 , wherein the frame includes a plurality of wiring layers, and

the plurality of wiring layers are electrically connected to the connection pad.

14. The semiconductor package of claim 13 , wherein the frame includes a first insulating layer in contact with the connection structure, a first wiring layer embedded in the first insulating layer and in contact with the connection structure, a second wiring layer disposed in a side of the first insulating layer opposite to a side of the first insulating layer in which the first wiring layer is embedded, a second insulating layer disposed on the first insulating layer and covering the second wiring layer, and a third wiring layer disposed on the second insulating layer,

the first to third wiring layers are electrically connected to the connection pad, and

a lower surface of the first insulating layer is coplanar with a lowermost surface of the protective film.

15. The semiconductor package of claim 13 , wherein the frame includes a first insulating layer, a first wiring layer disposed on a lower surface of the first insulating layer, a second wiring layer disposed on an upper surface of the first insulating layer, a second insulating layer disposed on the lower surface of the first insulating layer and covering the first wiring layer, a third wiring layer disposed on a lower surface of the second insulating layer, a third insulating layer disposed on the upper surface of the first insulating layer and covering the second wiring layer, and a fourth wiring layer disposed on an upper surface of the third insulating layer,

the first to fourth wiring layers are electrically connected to the connection pad, and

a lower surface of the third wiring layer is coplanar with a lowermost surface of the protective film.

16. The semiconductor package of claim 1 , wherein the semiconductor package is a fan-out semiconductor package.

17. The semiconductor package of claim 1 , wherein the connection via is spaced apart from the passivation film.

18. The semiconductor package of claim 1 , wherein the protective film is made of one or more of SiO x , SiN x , TiO 2 , ZnO, Al 2 O 3 , or polymers.

19. The semiconductor package of claim 1 , wherein a thickness of the protective film is about 1 nm to about 500 nm.