Semiconductor package
A semiconductor package includes a support frame, and including a cavity, a semiconductor chip disposed in the cavity and having an active surface on which contact pads are arranged, and a connection member on the support frame and on the active surface of the semiconductor chip. The semiconductor chip includes a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and having an outer peripheral region extending to a portion of the second insulating film around the first opening. The connection member includes an insulating layer including a second opening exposing the connection regions; and a redistribution layer connected to the contact pads through the second opening.
1. A semiconductor package comprising:
a support frame having a first surface and a second surface opposing each other, and including a cavity connecting the first and second surfaces;
a semiconductor chip disposed in the cavity, and having an active surface on which contact pads are arranged; and
a connection member disposed on the second surface of the support frame and on the active surface of the semiconductor chip,
wherein the semiconductor chip includes:
a first insulating film disposed on the active surface and exposing the contact pads; a RDL pattern connected to the contact pads and extending onto the first insulating film; a second insulating film disposed on the active surface and including a first opening exposing a connection region of the RDL pattern; and a conductive crack preventing layer disposed on the connection region and having an outer peripheral region extending to a portion of the second insulating film around the first opening, and
the connection member includes:
an insulating layer disposed on the second surface of the support frame and on the active surface of the semiconductor chip and including a second opening exposing the connection region, and a redistribution layer connected to the connection region through the second opening.
2. The semiconductor package of claim 1 , wherein the outer peripheral region of the conductive crack preventing layer is disposed between the insulating layer and the second insulating film.
3. The semiconductor package of claim 1 , wherein the outer peripheral region of the conductive crack preventing layer has a width of at least 5 μm.
4. The semiconductor package of claim 3 , wherein the width of the conductive crack preventing layer is a distance between an edge of the conductive crack preventing layer and the first opening measured along a line passing through a center of the first opening and a center of the second opening.
5. The semiconductor package of claim 1 , wherein the conductive crack preventing layer has a thickness equal to 1 μm or less.
6. The semiconductor package of claim 1 , wherein the conductive crack preventing layer comprises at least one of titanium (Ti) or tungsten (W).
7. The semiconductor package of claim 1 , wherein the second opening has an area larger than an area of the first opening, and partially exposes the outer peripheral region of the conductive crack preventing layer.
8. The semiconductor package of claim 1 , wherein the redistribution layer comprises a seed layer and a plating layer disposed on the seed layer.
9. The semiconductor package of claim 8 , wherein the conductive crack preventing layer is formed of the same material as a material of the seed layer.
10. The semiconductor package of claim 9 , wherein the conductive crack preventing layer and the seed layer are a titanium/tungsten (Ti/W) layer or a titanium/copper (Ti/Cu) layer.
11. The semiconductor package of claim 1 , wherein the first insulating film comprises at least one of an oxide or a nitride.
12. The semiconductor package of claim 1 , wherein the second insulating film comprises an organic insulating material.
13. The semiconductor package of claim 12 , wherein the connection member includes an additional insulating layer disposed on the redistribution layer, and an additional redistribution layer connected to the redistribution layer through the additional insulating layer.
14. The semiconductor package of claim 1 , wherein the second insulating film comprises a non-photoimageable dielectric material, and the insulating layer comprises a photoimageable dielectric material.
15. A semiconductor package comprising:
a support frame having a first surface and a second surface opposing each other, and including a cavity connecting the first and second surfaces;
a semiconductor chip disposed in the cavity, and having an active surface on which contact pads are arranged;
a connection member disposed on the second surface of the support frame and on the active surface of the semiconductor chip; and
an encapsulant encapsulating the semiconductor chip disposed in the cavity,
wherein the semiconductor chip includes:
a first insulating film disposed on the active surface and exposing the contact pads, a second insulating film disposed on the first insulating film and including a first opening exposing connection regions of the contact pads, and a conductive crack preventing layer disposed on the connection regions and extending to a portion of the second insulating film around the first opening, and
wherein the connection member includes:
an insulating layer disposed on the second surface of the support frame and on the active surface of the semiconductor chip, and including a second opening exposing the connection regions, the second opening being greater than the first opening; and a redistribution layer connected to the connection regions through the second opening.
16. The semiconductor package of claim 15 , wherein the second opening has an area larger than an area of the first opening, and
the conductive crack preventing layer extends to between the insulating layer and the second insulating film.