Redriver to autonomously detect cable orientation

1. A host system comprising:

a plurality of channels configured to be coupled to an interface, wherein each of the plurality of channels has a channel capacitor;

a plurality of detectors coupled to the plurality of channels, wherein the plurality of detectors are configured to output respective line voltages on the plurality of channels and measure charge rates of the channel capacitors to detect the presence or absence of termination resistors coupled to the respective channel capacitors; and

a controller configured to determine an orientation of the interface based on states detected by the plurality of detectors based upon the detected presence or absence of the termination resistors coupled to the respective channel capacitors by comparing the measured charge rates of the channel capacitors to charge rates of the channel capacitors when the termination resistors are absent, the controller configured to determine that the interface is in a normal orientation when a first combination of termination resistors is detected for the plurality of channels and to determine that the interface is in a second orientation when a second combination of termination resistors is detected for the plurality of channels, wherein the second orientation of the interface is a flipped version of the normal orientation of the interface.

2. The host system of claim 1 , wherein:

a first lane includes first and second channels of the plurality of channels, and

a second lane includes third and fourth channels of the plurality of channels, and the host system includes at least two lanes including the first lane and the second lane.

3. The host system of claim 2 , wherein a first combination of states includes:

the first channel and the second channel having a first state; and

the third channel and the fourth channel having a second state.

4. The host system of claim 3 , wherein a second combination of states includes:

the first channel and the second channel having the second state; and

the third channel and the fourth channel having the first state.

5. The host system of claim 2 , wherein a first combination of states includes:

the first channel having a first state and the second, third, and fourth channels having a second state after a timer period has expired; or

the second channel having the first state and the first, third, and fourth channels having the second state after the timer period has expired.

6. The host system of claim 5 , wherein the second combination of states includes:

the third channel having the first state and the first, second, and fourth channels having the second state after the timer period has expired; or

the fourth channel having the first state and the first, second, and third channels having the second state after the timer period has expired.

7. The host system of claim 2 , wherein a first combination of states includes:

the first, second, and third channels in a first state and the fourth channel in a second state; or

the first, second, and fourth channels in the first state and the third channel in the second state.

8. The host system of claim 7 , wherein the second combination of states includes:

the first, third, and fourth channels in the first state and the second channel in the second state; or

the second, third, and fourth channels in the first state and the first channel in the second state.

9. The host system of claim 1 , wherein the controller is configured to output a stimulus and the plurality of detectors are configured to detect the states in response to the stimulus.

10. The host system of claim 1 , wherein the plurality of detectors are configured to detect the states in response to an externally applied stimulus.

11. The host system of claim 10 , wherein the plurality of detectors are configured to detect the states in response to low frequency periodic signals (LFPS) or Loss of Signal (LoS) signals.

12. The host system of claim 1 , wherein the controller is configured to output at least one control signal to disable one or more of the plurality of channels not in use for the normal orientation or the second orientation.

13. The host system of claim 1 , wherein the controller is configured to output a notification signal to a processor or controller of a host, the notification signal indicating that the interface is in the normal orientation or the second orientation.

14. The host system of claim 1 , wherein:

each of the first and second combinations of states includes a first state and a second state;

the first state corresponds to detection of a terminal resistor; and

the second state corresponds to when the terminal resistor is not detected.

15. The host system of claim 1 , wherein the interface is a USB-C cable.

16. A method, comprising:

detecting, by a detector, states of a plurality of channels corresponding to an interface between a host system and a device, wherein each of the plurality of channels has a channel capacitor and detecting the states of the plurality of channels includes:

outputting respective line voltages on the plurality of channels; and

measuring charge rates of the channel capacitors to detect the presence or absence of termination resistors coupled to respective channel capacitors;

determining an orientation of the interface based on states detected by the plurality of detectors based upon the detected presence or absence of the termination resistors coupled to the respective channel capacitors by comparing the measured charge rates of the channel capacitors to charge rates of the channel capacitors when the termination resistors are absent;

determining that the interface has a normal orientation in response to detecting a first combination of termination resistors for the plurality of channels; and

determining that the interface has a second orientation in response to detecting a second combination of termination resistors for the plurality of channels, wherein the second orientation of the interface is a flipped version of the normal orientation of the interface.

17. The method of claim 16 , wherein:

each of a first combination of states and the second combination of states includes a first state and a second state;

the first state corresponds to detection of a terminal resistor; and

the second state corresponds to when the terminal resistor is not detected.

18. The host system of claim 1 , comprising:

a state table storing information relating a first combination of channel states to a normal orientation of the interface and a second combination of channel states to a second orientation of the interface.

19. The host system of claim 18 , wherein the controller is configured to output a notification signal to a processor or controller of the host system indicating that the interface is in the normal orientation or the second orientation.