Semiconductor package

1. A semiconductor package, comprising:

a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface, and including a passivation film disposed on the active surface and having a first opening exposing at least a portion of the connection pad and a protective film disposed on the passivation film, filling at least a portion in the first opening, and having a second opening exposing at least a portion of the connection pad in the first opening;

an encapsulant covering at least a portion of the semiconductor chip; and

a connection structure including an insulating layer disposed on the protective film, and having a via hole connected to the second opening to expose at least a portion of the connection pad, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer while filling at least a portion of each of the via hole and the second opening,

wherein the second opening and the via hole are connected to have a stepped portion,

wherein the first opening has a width narrower closer to the connection pad, and

wherein the second opening has a width wider closer to the connection pad.

2. The semiconductor package of claim 1 , wherein a wall surface of the second opening is recessed toward a wall surface of the first opening,

the recessed region is disposed between the insulating layer and the connection pad, and

the connection via fills at least a portion of the recessed region.

3. The semiconductor package of claim 2 , wherein the protective film and the insulating layer include different materials.

4. The semiconductor package of claim 1 , wherein, in a connection point of the second opening and the via hole, a width of the second opening is greater than a width of via hole.

5. The semiconductor package of claim 4 , wherein the second opening and the via hole are tapered in opposite directions.

6. The semiconductor package of claim 4 , wherein

the via hole has a width narrower closer to the connection pad.

7. The semiconductor package of claim 1 , wherein a region, excluding a region exposed by the second opening, of a region exposed by the first opening of the connection pad, is covered by a bent portion of the protective film in contact with the connection pad in the first opening.

8. The semiconductor package of claim 7 , wherein the insulating layer is physically spaced apart from the connection pad.

9. The semiconductor package of claim 1 , wherein the passivation film and the protective film are disposed in a region inside the active surface.

10. The semiconductor package of claim 9 , wherein the encapsulant covers a side surface of each of the passivation film and the protective film.

11. The semiconductor package of claim 9 , wherein the encapsulant fills a portion between the protective film and the insulating layer.

12. The semiconductor package of claim 1 , wherein the protective film has a thickness thinner than a thickness of the passivation film.

13. The semiconductor package of claim 1 , further comprising: a frame having a through-hole,

wherein the semiconductor chip is disposed in the through-hole,

the encapsulant covers at least a portion of the frame, and

the encapsulant fills at least a portion of the through-hole.

14. The semiconductor package of claim 13 , wherein the frame includes a first insulating layer in contact with the connection structure, a first wiring layer in contact with the connection structure and embedded in the first insulating layer, a second wiring layer disposed on a side of the first insulating layer opposite to a side of the first insulating layer in which the first wiring layer is embedded, a second insulating layer covering the second wiring layer and disposed on the first insulating layer, and a third wiring layer disposed on the second insulating layer,

the first to third wiring layers are electrically connected to the connection pad, and

a lower surface of the first insulating layer is coplanar with a lowermost surface of the protective film.

15. The semiconductor package of claim 13 , wherein the frame includes a first insulating layer, a first wiring layer disposed on a lower surface of the first insulating layer, a second wiring layer disposed on an upper surface of the first insulating layer, a second insulating layer disposed on the lower surface of the first insulating layer and covering the first wiring layer, a third wiring layer disposed on a lower surface of the second insulating layer, a third insulating layer disposed on the upper surface of the first insulating layer and covering the second wiring layer, and a fourth wiring layer disposed on an upper surface of the third insulating layer,

the first to fourth wiring layers are electrically connected to the connection pad, and

a lower surface of the third wiring layer is coplanar with a lowermost surface of the protective film.

16. The semiconductor package of claim 1 , wherein the semiconductor package is a fan-out semiconductor package.

17. A semiconductor package, comprising:

a semiconductor chip having an active surface on which a connection pad is disposed and an inactive surface opposite to the active surface;

an encapsulant covering at least a portion of the semiconductor chip;

a connection structure including an insulating layer disposed on the semiconductor chip, a redistribution layer disposed on the insulating layer, and a connection via connecting the connection pad to the redistribution layer;

a protective film disposed between the connection pad and the insulating layer; and

a passivation film disposed between the connection pad and the protective film,

wherein the connection via has a portion having a width smaller than a width of an uppermost portion of the connection via in contact with the connection pad and a width of a lowermost portion of the connection via in contact with the redistribution layer,

wherein the passivation film has a first opening exposing a portion of the connection pad,

wherein the protective film fills at least a portion in the first opening and has a second opening exposing a portion of the connection pad in the first opening, and

wherein the protective film includes a bent portion in contact with the connection pad in the first opening.

18. The semiconductor package of claim 17 , wherein the insulating layer is physically spaced apart from the connection pad.

19. The semiconductor package of claim 17 ,

wherein the portion of the connection pad exposed by the passivation film has a width greater than the portion of the connection pad exposed by the protective film.

20. The semiconductor package of claim 19 , wherein the encapsulant fills a portion between the protective film and the insulating layer.