Hardware security module

1. A hardware security module comprising:

two or more hardware ports, each one of which operable to electronically receive given input hardware port-specific cryptographic data thereon to initiate execution of an internal cryptographic process as a function thereof;

two or more segregated hardware port-specific storage spaces each operatively linked to a corresponding hardware port via a corresponding hardware link, and storing respective secured hardware port-specific cryptographic data thereon exclusively retrievable upon said given input hardware port-specific cryptographic data being received via said corresponding hardware port, wherein a given segregated hardware port-specific storage space is exclusively accessible in hardware, independent of said given input hardware port-specific cryptographic data, via said corresponding hardware link;

a cryptographic engine operable to execute said cryptographic process based on said secured port-specific cryptographic data retrieved from said segregated hardware port-specific storage spaces as a function of said given input port-specific cryptographic data;

wherein said cryptographic engine comprises distinct hardware port-specific cryptographic engines;

wherein each of said distinct hardware port-specific cryptographic engines is associated with a corresponding one of said segregated hardware-port specific storage spaces;

wherein said corresponding one of said segregated hardware-port specific storage spaces is exclusively accessible via a hardware link operatively defined through said associated one of said distinct hardware port-specific cryptographic engines; and

wherein the hardware security module further comprises a hardwired port interconnection matrix that operatively interconnects at least some of said hardware ports in accordance with predefined hardwired port-specific logic.

2. The hardware security module of claim 1 , wherein said corresponding hardware link is physically segregated such that a designated hardware-port-specific storage space is inaccessible in hardware upon said given input hardware port-specific data being received via a distinct hardware port.

3. The hardware security module of claim 1 , wherein each said segregated hardware port-specific storage space is physically isolated in hardware from any other said segregated hardware port-specific storage space.

4. The hardware security module of claim 1 , wherein each of said segregated hardware port-specific storage spaces comprises distinctly embedded storage media operatively hardwired to said corresponding one of said hardware ports.

5. The hardware security module of claim 1 , wherein each of said segregated hardware port-specific storage spaces comprises distinct partitions of a common embedded storage media each operatively hardwired to said corresponding one of said hardware ports.

6. The hardware security module of claim 1 , further comprising an embedded processing system operable to execute said cryptographic engine, wherein said embedded processing system comprises a dedicated processing core, and wherein said hardware ports, said segregated hardware port-specific storage spaces and said cryptographic engine are hardwired within a common integrated circuit architecture.

7. The hardware security module of claim 6 , wherein said common integrated circuit architecture is implemented in a field-programmable gate array (FPGA).

8. The hardware security module of claim 1 , wherein said interconnection matrix is reconfigurable to redefine said hardwired port-specific logic.

9. The hardware security module of claim 8 , wherein said port interconnection matrix is further configured to invoke one or more embedded communication channel resources operable on selected hardware port-specific data communicated via said matrix.

10. The hardware security module of claim 1 , wherein said two or more segregated hardware port-specific storage spaces comprise one or more externally integrated hardware storage resources.

11. A hardware security module comprising:

two or more hardware ports, each one of which operable to electronically receive given input hardware port-specific cryptographic data thereon to initiate execution of an internal cryptographic process as a function thereof;

two or more segregated hardware port-specific storage spaces, each physically isolated in hardware from any other of said segregated hardware port-specific storage spaces, operatively linked to a corresponding hardware port via a corresponding hardware link, and storing respective secured hardware port-specific cryptographic data thereon exclusively retrievable upon said given input hardware port-specific cryptographic data corresponding thereto and being received via said corresponding one of said hardware ports such that said respective secured hardware port-specific cryptographic data is inaccessible in hardware upon said given input hardware port-specific data being received via a distinct hardware port;

a cryptographic engine operable to execute said cryptographic process based on said secured port-specific cryptographic data retrieved from said segregated hardware port-specific storage spaces as a function of said given input port-specific cryptographic data;

wherein the hardware security module further comprises a hardwired port interconnection matrix that operatively interconnects at least some of said hardware ports in accordance with predefined hardwired port-specific logic;

wherein said port interconnection matrix is further configured to invoke one or more embedded communication channel resources operable on selected hardware port-specific data communicated via said matrix.

12. The hardware security module of claim 11 , wherein a given segregated hardware port-specific storage space is exclusively accessible in hardware, independent of said given input hardware port-specific cryptographic data, via said corresponding hardware link.

13. The hardware security module of claim 11 , wherein each of said segregated hardware port-specific storage spaces comprises distinctly embedded storage media operatively hardwired to said corresponding one of said hardware ports.

14. The hardware security module of claim 11 , wherein a same said cryptographic engine is commonly operable to execute a same said cryptographic process for each of said secured port-specific cryptographic data irrespective of hardware port-specificity.

15. The hardware security module of claim 11 , wherein said cryptographic engine comprises distinct hardware port-specific cryptographic engines.

16. The hardware security module of claim 15 , wherein each of said distinct hardware port-specific cryptographic engines is associated with a corresponding one of said segregated hardware-port specific storage spaces.

17. The hardware security module of claim 16 , wherein said corresponding one of said segregated hardware-port specific storage spaces is exclusively accessible via a hardware link operatively defined through said associated one of said distinct hardware port-specific cryptographic engines.

18. The hardware security module of claim 11 , wherein said interconnection matrix is reconfigurable to redefine said hardwired port-specific logic.

19. The hardware security module of claim 11 , wherein said two or more segregated hardware port-specific storage spaces comprise one or more externally integrated hardware storage resources.