IP Library › Granted Patent US 10,943,991
Granted Patent B2
US 10,943,991 · App. 16/294,877 · Granted Mar 9, 2021

Semiconductor device and method for fabricating the same

Inventors: Wei-Chih Chuang (Tainan, TW); Chia-Jong Liu (Ping-Tung County, TW); Kuang-Hsiu Chen (Tainan, TW); Chung-Ting Huang (Kaohsiung, TW); Chi-Hsuan Tang (Kaohsiung, TW); Kai-Hsiang Wang (Taichung, TW); Bing-Yang Jiang (Tainan, TW); Yu-Lin Cheng (Changhua County, TW); Chun-Jen Chen (Tainan, TW); Yu-Shu Lin (Pingtung County, TW); Jhong-Yi Huang (Nantou County, TW); Chao-Nan Chen (Tainan, TW); Guan-Ying Wu (Kaohsiung, TW)
Assignee: UNITED MICROELECTRONICS CORP.
H01L29/6656H01L29/42364
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Quick Facts
Patent No.
US 10,943,991
App. No.
16/294,877
Granted
Mar 9, 2021
Kind
B2
Abstract

A semiconductor device and a method for fabricating the semiconductor device are provided, in which the method includes the steps of forming a gate structure on a substrate, forming a spacer on a sidewall of the gate structure, forming two recesses adjacent to two sides of the spacer, performing a cleaning process to trim the spacer for forming a void between the spacer and the substrate, and forming two portions of an epitaxial layer in the two recesses. The semiconductor device preferably includes a cap layer on the two portions of the epitaxial layer as the cap layer includes a planar top surface and an inclined sidewall.

Claims (18)

1. A semiconductor device, comprising:

a gate structure on a substrate;

a first spacer on a sidewall of the gate structure;

a second spacer on a sidewall of the first spacer;

a third spacer on a sidewall of the second spacer; and

first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure, wherein the cap layer comprises a planar top surface and an inclined sidewall, the cap layer contacts the second spacer and the third spacer directly, and the cap layer comprises a vertical sidewall connected to the inclined sidewall.

2. The semiconductor device of claim 1 , wherein the first spacer comprises an I-shape, the second spacer comprises an L-shape, and the third spacer comprises a lower portion with an I-shape and an upper portion with a half-arc shape.

3. The semiconductor device of claim 2 , wherein a bottom surface of the third spacer is higher than a bottom surface of the second spacer.

4. The semiconductor device of claim 2 , wherein bottom surfaces of the first spacer and the gate structure are coplanar.

5. The semiconductor device of claim 2 , wherein bottom surfaces of the second spacer and the gate structure are coplanar.

6. The semiconductor device of claim 1 , wherein the first spacer comprises silicon oxide and the second spacer comprises silicon nitride.

7. The semiconductor device of claim 1 , wherein the cap layer comprises silicon.

8. A semiconductor device, comprising:

a gate structure on a substrate;

a first spacer on a sidewall of the gate structure;

a second spacer on a sidewall of the first spacer;

a third spacer on a sidewall of the second spacer;

first and second stacks of an epitaxial layer and a cap layer respectively disposed at first and second sides of the gate structure, wherein the cap layer comprises a planar top surface, an inclined sidewall, and a vertical sidewall connected to the inclined sidewall.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 6, 2019
From: CHUANG, WEI-CHIH; LIU, CHIA-JONG; CHEN, KUANG-HSIU; HUANG, CHUNG-TING; TANG, CHI-HSUAN; WANG, KAI-HSIANG; JIANG, BING-YANG; CHENG, YU-LIN; CHEN, CHUN-JEN; LIN, YU-SHU; HUANG, JHONG-YI; CHEN, CHAO-NAN; WU, GUAN-YING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 048525/0001 →
Priority Claims (1)
TW 108103436 · Jan 30, 2019 · national
Continuity (1)
Related Publication 20200243664A1 · Jul 30, 2020
Cited By (1)
US 12,356,677