NAND logic gate with data-independent delay
Devices and methods are presented for supplying logic gate signals with a data-independent delay. The method provides a logic gate comprising a pull-up network connected to a pull-down network. The method supplies binary level digital data input signals to the pull-up network and pull-down network, which may be either single-ended or complementary. The pull-up network and pull-down network regulate current through the logic gate with a delay and impedance independent of the data signals. As a result, the logic gate supplies binary level digital logic output signals in response to the data input signals, with a uniform delay. For example, the logic gates may be one of the following: NOR gate, NAND gate, AND gate, or OR gate.
1. A NAND logic integrated circuit (IC) with data-independent delay, the NAND logic IC comprising:
a pull-up network having an input to accept binary level digital data input signals, an output to supply binary level digital logic output signals responsive to the data input signals, and a current interface connected to a first reference voltage;
a pull-down network having an input to accept the data input signals, a current interface connected to a second reference voltage having a lower potential than the first reference voltage, and an output connected to the output of pull-up network;
wherein the pull-up network and the pull-down network maintain a uniform impedance between their respective outputs and current interfaces, independent of the data input signals, when enabled;
wherein the pull-down network comprises:
a first NMOS having a first S/D connected to the output to supply NAND logic signals, a gate to accept a first single-ended data input signal (a), and a second S/D; and,
a second NMOS having a first S/D connected to the second S/D of the first NMOS, a gate to accept a second single-ended data input signal (b), and a second S/D connected to the second reference voltage;
wherein the pull-up network comprises:
a first PMOS with a first S/D connected to the first reference voltage, a gate to accept the second single-ended data input signal, and a second S/D connected to the output;
a second PMOS with a first S/D connected to the first reference voltage, a gate to accept the first single-ended data input signal, and a second S/D connected to the output;
a third PMOS with a first S/D connected to the first reference voltage, a gate to accept the first single-ended data input signal, and a second S/D;
a third NMOS with a first S/D connected to the second S/D of the third PMOS, a gate to accept the second single-ended data input signal, and a second S/D connected to the output;
a fourth PMOS with a first S/D connected to the first reference voltage, a gate to accept the second single-ended data input signal, and a second S/D;
a fourth NMOS with a first S/D connected to the second S/D of the fourth PMOS, a gate to accept the first single-ended data input signal, and a second S/D connected to the output; and,
wherein the pull-up network creates uniform rise time delays in the logic output signals, responsive to the single-ended data input signals.
2. The NAND logic IC of claim 1 further comprising:
an inverter connected to the output of the pull-up network to accept NAND logic output signals (y), and having an output to supply single-ended AND logic output signals (y_bar).
3. A NAND logic integrated circuit (IC) with data-independent delay, the NAND logic IC comprising:
a pull-up network having an input to accept binary level digital data input signals, an output to supply binary level digital logic output signals responsive to the data input signals, and a current interface connected to a first reference voltage;
a pull-down network having an input to accept the data input signals, a current interface connected to a second reference voltage having a lower potential than the first reference voltage, and an output connected to the output of pull-up network;
wherein the pull-up network and the pull-down network maintain a uniform impedance between their respective outputs and current interfaces, independent of the data input signals, when enabled;
wherein pull-down network comprises:
a first NMOS having a first S/D connected to the output to supply NAND logic signals, a gate to accept a first non-inverted complementary data input signal (a), and a second S/D; and,
a second NMOS having a first S/D connected to the second S/D of the first NMOS, a gate to accept a second non-inverted complementary data input signal (b), and a second S/D connected to the second reference voltage;
wherein the pull-up network comprises:
a first PMOS with a first S/D connected to the first reference voltage, a gate to accept the second non-inverted complementary data input signal, and a second S/D connected to the output;
a second PMOS with a first S/D connected to the first reference voltage, a gate to accept the first non-inverted complementary data input signal, and a second S/D connected to the output;
a third PMOS with a first S/D connected to the first reference voltage, a gate to accept a first inverted complementary data input signal (a_bar), and a second S/D;
a fourth PMOS with a first S/D connected to the second S/D of the third PMOS, a gate to accept the second non-inverted complementary data input signal, and a second S/D connected to the output;
a fifth PMOS with a first S/D connected to the first reference voltage, a gate to accept a second inverted complementary data input signal (b_bar), and a second S/D;
a sixth PMOS with a first S/D connected to the second S/D of the fifth PMOS, a gate to accept the first non-inverted complementary data input signal, and a second S/D connected to the output; and,
wherein the pull-up network creates uniform rise time delays in the logic output signals, responsive to the complementary data input signals.
4. The NAND logic IC of claim 2 wherein the combination of the (y) and (y_bar) logic output signals are interpreted as logic output signals selected from the group consisting of complementary AND logic output signals or complementary NAND logic output signals.
5. The logic IC of claim 3 further comprising:
an inverter connected to the output of the pull-up network to accept logic output signals (y), and having an output to supply single-ended binary level digital AND logic output signals (y_bar).
6. The NAND logic IC of claim 5 wherein the combination of the (y) and (y_bar) logic output signals are interpreted as logic output signals selected from the group consisting of complementary AND logic output signals or complementary NAND logic output signals.